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The 8085 Microprocessor Architecture

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Bus organization of 8085 microprocessor

Introduction :

The bus organization of the 8085 microprocessor is the way in which the microprocessor communicates with other devices in a computer system. The 8085 microprocessor has a 16-bit address bus, an 8-bit data bus, and various control signals that are used to manage data transfer and other operations.

The address bus is used to specify the memory location or device with which the microprocessor wants to communicate. It is 16 bits wide, which allows the microprocessor to address up to 64K bytes of memory. The address bus is unidirectional, which means that data can only flow in one direction from the microprocessor to the addressed device.

The data bus is used to transfer data between the microprocessor and other devices. It is 8 bits wide, which means that data can be transferred in byte-sized chunks. The data bus is bidirectional, which means that data can flow in either direction between the microprocessor and other devices.

In addition to the address and data buses, the 8085 microprocessor has various control signals that are used to manage data transfer and other operations. These control signals include the read (RD), write (WR), and hold (HLDA) signals, among others. The RD and WR signals are used to control data transfer to and from memory or other devices, while the HLDA signal is used to indicate that the microprocessor is in a hold state and cannot execute instructions.

 There are several reasons why bus organization is used in the 8085 microprocessor:

• Memory access: The bus organization is used for accessing memory by transferring the address of the memory location through the address bus and the data to be stored or retrieved through the data bus. This enables the microprocessor to read and write data to and from memory, which is essential for executing instructions and storing data.
• I/O operations: The bus organization is used for performing input/output (I/O) operations by transferring the input/output device address through the address bus and the data to be input or output through the data bus. This enables the microprocessor to communicate with peripheral devices such as keyboards, displays, and sensors.
• Interrupt handling: The bus organization is used for interrupt handling, where the microprocessor uses the address bus to fetch the interrupt vector and the data bus to fetch the interrupt service routine. This enables the microprocessor to respond to external events and perform time-critical operations.
• DMA operations: The bus organization is used for performing Direct Memory Access (DMA) operations, where the data transfer between the memory and I/O devices takes place without the intervention of the microprocessor. This enables high-speed data transfer between devices and reduces the load on the microprocessor.
• Control signal transfer: The bus organization is used for transferring control signals between the microprocessor and other components of the system. This enables the microprocessor to control the operation of devices and coordinate the execution of instructions.

There are three types of buses.

• Address bus –  

The address bus is a unidirectional bus that is used to carry the memory or I/O device address to which the data is to be transferred. The address bus in the 8085 microprocessor is 16-bit wide.

It is a group of conducting wires which carries address only.Address bus is unidirectional because data flow in one direction, from microprocessor to memory or from microprocessor to Input/output devices (That is, Out of Microprocessor). Length of Address Bus of 8085 microprocessor is 16 Bit (That is, Four Hexadecimal Digits), ranging from 0000 H to FFFF H, (H denotes Hexadecimal). The microprocessor 8085 can transfer maximum 16 bit address which means it can address 65, 536 different memory location. The Length of the address bus determines the amount of memory a system can address.Such as a system with a 32-bit address bus can address 2^32 memory locations.If each memory location holds one byte, the addressable memory space is 4 GB.However, the actual amount of memory that can be accessed is usually much less than this theoretical limit due to chipset and motherboard limitations.

• Data bus –

The data bus is an 8-bit bidirectional bus that is used to transfer data between the microprocessor and other components such as memory and I/O devices. It is used to carry data to or from the memory or input/output devices.

 It is a group of conducting wires which carries Data only.Data bus is bidirectional because data flow in both directions, from microprocessor to memory or Input/Output devices and from memory or Input/Output devices to microprocessor. Length of Data Bus of 8085 microprocessor is 8 Bit (That is, two Hexadecimal Digits), ranging from 00 H to FF H. (H denotes Hexadecimal). When it is write operation, the processor will put the data (to be written) on the data bus, when it is read operation, the memory controller will get the data from specific memory block and put it into the data bus. The width of the data bus is directly related to the largest number that the bus can carry, such as an 8 bit bus can represent 2 to the power of 8 unique values, this equates to the number 0 to 255.A 16 bit bus can carry 0 to 65535.

• Control bus –  

The control bus is a bidirectional bus that is used to carry control signals between the microprocessor and other components such as memory and I/O devices. It is used to transmit commands to the memory or I/O devices for performing specific operations.

It is a group of conducting wires, which is used to generate timing and control signals to control all the associated peripherals, microprocessor uses control bus to process data, that is what to do with selected memory location. Some control signals are:

Memory read

Memory write

• Opcode fetch

Uses of Bus organization in 8085 microprocessor :

Some of the important uses of bus organization in the 8085 microprocessor are:

• Memory access: The bus organization is used for accessing the memory by transferring the address of the memory location through the address bus and the data to be stored or retrieved through the data bus.
• I/O operations: The bus organization is used for performing input/output operations by transferring the input/output device address through the address bus and the data to be input or output through the data bus.
• Interrupt handling: The bus organization is used for interrupt handling, where the microprocessor uses the address bus to fetch the interrupt vector and the data bus to fetch the interrupt service routine.
• DMA operations: The bus organization is used for performing Direct Memory Access (DMA) operations, where the data transfer between the memory and I/O devices takes place without the intervention of the microprocessor.

Advantages:

Flexibility: The bus organization used in the 8085 microprocessor allows it to communicate with a wide range of devices. This flexibility makes it well-suited for use in a variety of computer systems, including embedded systems, personal computers, and other devices.

Modularity: The bus organization makes it easy to add or remove devices from a computer system. This modularity allows system designers to customize the system to meet the needs of specific applications.

Scalability: The bus organization used in the 8085 microprocessor is scalable, which means that it can be used in systems of varying sizes and complexity. This scalability makes it well-suited for use in systems that require a wide range of performance levels.

Low Cost: The bus organization used in the 8085 microprocessor is relatively simple and inexpensive to implement. This makes it an attractive option for low-cost, embedded applications.

Disadvantages:

Limited Bandwidth: The bus organization used in the 8085 microprocessor has a limited bandwidth, which can limit the performance of the processor in high-performance applications.

Latency: The bus organization can introduce latency, which is the delay between the time a command is issued and the time the response is received. This latency can be a problem in real-time applications that require immediate responses.

Data Integrity: The bus organization used in the 8085 microprocessor is vulnerable to data corruption due to electromagnetic interference and other sources of noise. This can lead to errors in data transmission and processing.

Complexity: The bus organization used in the 8085 microprocessor can be complex to implement and troubleshoot, which can increase the cost and time required to develop and maintain computer systems.

Issues of Bus organization in 8085 microprocessor :

Some of the main issues with bus organization in the 8085 microprocessor are:

• Limited data transfer rate: The 8085 microprocessor has an 8-bit data bus, which means that it can transfer only 8 bits of data at a time. This limited data transfer rate can be a bottleneck in systems that require faster data transfer.
• Limited address range: The 8085 microprocessor has a 16-bit address bus, which limits the addressable memory to 64 KB. This can be a limitation in systems that require larger memory addressing.
• Bus contention: Bus contention occurs when two or more devices try to use the bus at the same time. This can cause data corruption and other errors in the system.
• Timing issues: The bus organization requires precise timing for the signals to be transmitted correctly. Any timing errors can cause data corruption or other errors in the system.
• Limited number of devices: The bus organization of the 8085 microprocessor can support a limited number of devices due to its limited bus width and address range. This can be a limitation in systems that require more devices to be connected.
• Noise interference: The signals on the bus can be affected by noise interference, which can cause errors in the system.
• Power consumption: The bus organization can consume significant power, especially when many devices are connected to the bus. This can be a limitation in portable or low-power systems.

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8085 Microprocessor:

Dec 19, 2019

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8085 Microprocessor:. Architecture & Support Components. Contents. Pin diagram of 8085 8085 Operations Architecture of 8085 8085 Communication with Memory. Pinout Diagram of 8085. A 40-pin IC Six groups of signals Address Bus Data Bus Control and Status pins

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8085 Microprocessor: Architecture & Support Components

Contents • Pin diagram of 8085 • 8085 Operations • Architecture of 8085 • 8085 Communication with Memory

Pinout Diagram of 8085 • A 40-pin IC • Six groups of signals • Address Bus • Data Bus • Control and Status pins • Power Supply & frequency signals • Externally initiated Signals • Serial I/O ports

Logic Pinout of 8085 Power Supply & frequency Data Bus Address Bus Serial I/O ports Externally initiated signals Control & Status Control & Status

8085 Operations • Microprocessor Initiated Operations • Internal Operations • Peripheral/Externally Initiated Operations

Microprocessor Initiated Operations • Memory Read • Memory Write • I/O Read • I/O Write

Internal Operations • Store 8-bit data • Perform Arithmetic and Logic Operations • Test for conditions • Sequence the execution of instructions • Store/Retrieve data from stack during execution

Peripheral/Externally Initiated Operations • Reset • Interrupt • Ready • Hold

Architecture of 8085 • Power Supply – a +5V DC power supply • Maximum clock frequency of 3MHz • 8-bit general purpose microprocessor • 16-bit Address Bus • Capable of addressing 64K of memory

Architecture of 8085

ALU Timing and Control Unit General Purpose Registers Program Status word Program Counter Stack Pointer Instruction Register and Decoder Interrupt Control Serial I/O Control Address Bus Data Bus Architecture 0f 8085 Cont…

Architecture 0f 8085 Cont… • Arithmetic Logic Unit (ALU) • 8085 has 8-bit ALU • Performs arithmetic & Logic operations on data • Timing & Control Unit • Generates timing and control signals • General Purpose Registers • 8-bit registers (B,C,D,E,H,L) • 16-bit register pairs (BC, DE, HL,PSW)

Architecture 0f 8085 Cont… • Program Status Word (PSW) • Accumulator and Flag Register can be combined as a register pair called PSW • Instruction Register and Decoder • Instruction fetched from memory is stored in Instruction register (8-bit register) • Decoder decodes the instruction and directs the Timing & Control Unit accordingly

Architecture 0f 8085 Cont… • Interrupt Control • 8085 has 5 interrupt signals • INTR – general purpose interrupt • RST 5.5 Restart Interrupts • RST 6.5 • RST 7.5 • TRAP – non-maskable interrupt • The interrupts listed above are in increasing order of priority

Architecture 0f 8085 Cont… • Serial I/O Control • 8085 has two signals for serial communication • SID – Serial Input Data • SOD – Serial Output Data

Architecture 0f 8085 Cont… • Address Bus • Used to address memory & I/O devices • 8085 has a 16-bit address bus Higher-order Address Lower-order Address Data Bus • Data Bus • Used to transfer instructions and data • 8085 has a 8-bit data bus

8085 Communication with Memory • Involves the following three steps • Identify the memory location (with address) • Generate Timing & Control signals • Data transfer takes place

Example: Memory Read Operation 1 3 2

Timing Diagram

Demultiplexing Address/Data Bus • 8085 identifies a memory location with its 16 address lines, (AD0 to AD7) & (A8 to A15) • 8085 performs data transfer using its data lines, AD0 to AD7 • Lower order address bus & Data bus are multiplexed on same lines i.e. AD0 to AD7. • Demultiplexing refers to separating Address & Data signals for read/write operations

Need for Demultiplexing… RD A8-A15 8085 Memory 20H AD0-AD7 05H 4FH 2005H

8085 Interfacing with Memory chips Address Address Memory Interface Memory Chip Data Data 8085 Control Control

8085 Interfacing with Memory chips Data Memory Chip 74LS373 8085 AD0-AD7 A0 – A7 ALE A8-A15 A8-A15 Control Memory Interface

8085 Interfacing with Memory chips Data Program Memory 74LS373 8085 AD0-AD7 A0 – A7 ALE A8-A15 A8-A15 CS IO/M RD RD Memory Interface

Memory Mapping • 8085 has 16-bit Address Bus • The complete address space is thus given by the range of addresses 0000H – FFFFH • The range of addresses allocated to a memory device is known as its memory map

Memory map: 64K memory device • Address lines required: 16 (A0 – A15) • Memory map: 0000H - FFFFH • So the memory map is A11 to A0 0…. 0 0 = 0000H to A11 to A0 1…. 111 = FFFFH

Interfacing I/O devices with 8085 Peripheral-mapped I/O & Memory-mapped I/O

Interfacing I/O devices with 8085 I/O Interface I/O Devices 8085 System Bus Memory Interface Memory Devices

Techniques for I/O Interfacing • Memory-mapped I/O • Peripheral-mapped I/O

Memory-mapped I/O • 8085 uses its 16-bit address bus to identify a memory location • Memory address space: 0000H to FFFFH • 8085 needs to identify I/O devices also • I/O devices can be interfaced using addresses from memory space • 8085 treats such an I/O device as a memory location • This is called Memory-mapped I/O

Peripheral-mapped I/O • 8085 has a separate 8-bit addressing scheme for I/O devices • I/O address space: 00H to FFH • This is called Peripheral-mapped I/O or I/O-mapped I/O

8085 Communication with I/O devices • Involves the following three steps • Identify the I/O device (with address) • Generate Timing & Control signals • Data transfer takes place • 8085 communicates with a I/O device only if there is a Program Instruction to do so

1.Identify the I/O device (with address) • Memory-mapped I/O (16-bit address) • Peripheral-mapped I/O (8-bit address)

2.Generate Timing & Control Signals • Memory-mapped I/O • Reading Input: IO/M = 0, RD = 0 • Write to Output: IO/M = 0, WR = 0 • Peripheral-mapped I/O • Reading Input: IO/M = 1, RD = 0 • Write to Output: IO/M = 1, WR = 0 3. Data transfer takes place

Peripheral I/O Instructions • IN Instruction • Inputs data from input device into the accumulator • It is a 2-byte instruction • Format: IN8-bit port address • Example: IN01H

OUT Instruction • Outputs the contents of accumulator to an output device • It is a 2-byte instruction • Format: OUT8-bit port address • Example: OUT02H

----------Example Program---------- • WAP to read a number from input port (port address 01H) and display it on ASCII display connected to output port (port address 02H) IN01H ;reads data value 03H (example)into ;accumulator, A = 03H MVI B, 30H;loads register B with 30H ADD B ;A = 33H, ASCII code for 3 OUT02H ;display 3 on ASCII display

Memory-mapped I/O Instructions • I/O devices are identified by 16-bit addresses • 8085 communicates with an I/O device as if it were one of the memory locations • Memory related instructions are used • For e.g. LDA, STA • LDA8000H • Loads A with data read from input device with 16-bit address 8000H • STA8001H • Stores (Outputs) contents of A to output device with 16-bit address 8001H

----------Example Program---------- • WAP to read a number from input port (port address 8000H) and display it on ASCII display connected to output port (port address 8001H) LDA8000H;reads data value 03H (example)into ;accumulator, A = 03H MVI B, 30H;loads register B with 30H ADD B ;A = 33H, ASCII code for 3 STA8001H;display 3 on ASCII display

Show the Pinout of 8085 in several grpups. • Mention the operations of 8085 in group • Discuss the data bus and address bus and the multiplexing. • Short questions

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The 8085 Microprocessor Architecture - PowerPoint PPT Presentation

The 8085 Microprocessor Architecture

The 8085 microprocessor architecture * * 8085 instruction set data transfer operations between registers between memory location and a register direct write to a ... – powerpoint ppt presentation.

• The typical processor system consists of
• CPU (central processing unit)
• ALU (arithmetic-logic unit)
• Control Logic
• Registers, etc
• Input / Output interfaces
• Interconnections between these units
• Address Bus
• Control Bus
• The internal architecture of the 8085 CPU is capable of performing the following operations
• Store 8-bit data (Registers, Accumulator)
• Perform arithmetic and logic operations (ALU)
• Test for conditions (IF / THEN)
• Sequence the execution of instructions
• Store temporary data in RAM during execution
• Six general purpose 8-bit registers B, C, D, E, H, L
• They can also be combined as register pairs to
• perform 16-bit operations BC, DE, HL
• Registers are programmable (data load, move, etc.)
• Accumulator
• Single 8-bit register that is part of the ALU !
• Used for arithmetic / logic operations the result is always stored in the accumulator.
• The Program Counter (PC)
• This is a register that is used to control the sequencing of the execution of instructions.
• This register always holds the address of the next instruction.
• Since it holds an address, it must be 16 bits wide.
• The Stack pointer
• The stack pointer is also a 16-bit register that is used to point into memory.
• The memory this register points to is a special area called the stack.
• The stack is an area of memory used to hold data that will be retreived soon.
• The stack is usually accessed in a Last In First Out (LIFO) fashion.
• The 8085 is an 8-bit general purpose microprocessor that can address 64K Byte of memory.
• It has 40 pins and uses 5V for power. It can run at a maximum frequency of 3 MHz.
• The pins on the chip can be grouped into 6 groups
• Address Bus.
• Control and Status Signals.
• Power supply and frequency.
• Externally Initiated Signals.
• Serial I/O ports.
• The 8-bit 8085 CPU (or MPU Micro Processing Unit) communicates with the other units using a 16-bit address bus, an 8-bit data bus and a control bus.
• The address bus has 8 signal lines A8 A15 which are unidirectional.
• The other 8 address bits are multiplexed (time shared) with the 8 data bits.
• So, the bits AD0 AD7 are bi-directional and serve as A0 A7 and D0 D7 at the same time.
• During the execution of the instruction, these lines carry the address bits during the early part, then during the late parts of the execution, they carry the 8 data bits.
• In order to separate the address from the data, we can use a latch to save the value before the function of the bits changes.
• There are 4 main control and status signals. These are
• ALE Address Latch Enable. This signal is a pulse that become 1 when the AD0 AD7 lines have an address on them. It becomes 0 after that. This signal can be used to enable a latch to save the address bits from the AD lines.
• RD Read. Active low.
• WR Write. Active low.
• IO/M This signal specifies whether the operation is a memory operation (IO/M0) or an I/O operation (IO/M1).
• S1 and S0 Status signals to specify the kind of operation being performed .Usually un-used in small systems.
• There are 3 important pins in the frequency control group.
• X0 and X1 are the inputs from the crystal or clock generating circuit.
• The frequency is internally divided by 2.
• So, to run the microprocessor at 3 MHz, a clock running at 6 MHz should be connected to the X0 and X1 pins.
• CLK (OUT) An output clock pin to drive the clock of the rest of the system.
• We will discuss the rest of the control signals as we get to them.
• To understand how the microprocessor operates and uses these different signals, we should study the process of communication between the microprocessor and memory during a memory read or write operation.
• Lets look at timing and the data flow of an instruction fetch operation. (Example 3.1)
• Lets assume that we are trying to fetch the instruction at memory location 2005. That means that the program counter is now set to that value.
• The following is the sequence of operations
• The program counter places the address value on the address bus and the controller issues a RD signal.
• The memorys address decoder gets the value and determines which memory location is being accessed.
• The value in the memory location is placed on the data bus.
• The value on the data bus is read into the instruction decoder inside the microprocessor.
• After decoding the instruction, the control unit issues the proper control signals to perform the operation.
• Now, lets look at the exact timing of this sequence of events as that is extremely important. (figure 3.3)
• At T1 , the high order 8 address bits (20H) are placed on the address lines A8 A15 and the low order bits are placed on AD7AD0. The ALE signal goes high to indicate that AD0 AD8 are carrying an address. At exactly the same time, the IO/M signal goes low to indicate a memory operation.
• At the beginning of the T2 cycle, the low order 8 address bits are removed from AD7 AD0 and the controller sends the Read (RD) signal to the memory. The signal remains low (active) for two clock periods to allow for slow devices. During T2 , memory places the data from the memory location on the lines AD7 AD0 .
• During T3 the RD signal is Disabled (goes high). This turns off the output Tri-state buffers in the memory. That makes the AD7 AD0 lines go to high impedence mode.
• From the above description, it becomes obvious that the AD7 AD0 lines are serving a dual purpose and that they need to be demultiplexed to get all the information.
• The high order bits of the address remain on the bus for three clock periods. However, the low order bits remain for only one clock period and they would be lost if they are not saved externally. Also, notice that the low order bits of the address disappear when they are needed most.
• To make sure we have the entire address for the full three clock cycles, we will use an external latch to save the value of AD7 AD0 when it is carrying the address bits. We use the ALE signal to enable this latch.
• Given that ALE operates as a pulse during T1, we will be able to latch the address. Then when ALE goes low, the address is saved and the AD7 AD0 lines can be used for their purpose as the bi-directional data lines.
• From the above discussion, we can define terms that will become handy later on
• T- State One subdivision of an operation. A T-state lasts for one clock period.
• An instructions execution length is usually measured in a number of T-states. (clock cycles).
• Machine Cycle The time required to complete one operation of accessing memory, I/O, or acknowledging an external request.
• This cycle may consist of 3 to 6 T-states.
• Instruction Cycle The time required to complete the execution of an instruction.
• In the 8085, an instruction cycle may consist of 1 to 6 machine cycles.
• The 8085 generates a single RD signal. However, the signal needs to be used with both memory and I/O. So, it must be combined with the IO/M signal to generate different control signals for the memory and I/O.
• Keeping in mind the operation of the IO/M signal we can use the following circuitry to generate the right set of signals
• Previously we discussed the 8085 from a programmers perspective.
• Now, lets look at some of its features with more detail.
• In addition to the arithmetic logic circuits, the ALU includes the accumulator, which is part of every arithmetic logic operation.
• Also, the ALU includes a temporary register used for holding data temporarily during the execution of the operation. This temporary register is not accessible by the programmer.
• There is also the flags register whose bits are affected by the arithmetic logic operations.
• S-sign flag
• The sign flag is set if bit D7 of the accumulator is set after an arithmetic or logic operation.
• Z-zero flag
• Set if the result of the ALU operation is 0. Otherwise is reset. This flag is affected by operations on the accumulator as well as other registers. (DCR B).
• AC-Auxiliary Carry
• This flag is set when a carry is generated from bit D3 and passed to D4 . This flag is used only internally for BCD operations. (Section 10.5 describes BCD addition including the DAA instruction).
• P-Parity flag
• After an ALU operation if the result has an even of 1s the p-flag is set. Otherwise it is cleared. So, the flag can be used to indicate even parity.
• CY-carry flag
• Discussed earlier
• The 8085 executes several types of instructions with each requiring a different number of operations of different types. However, the operations can be grouped into a small set.
• The three main types are
• Memory Read and Write.
• I/O Read and Write.
• Request Acknowledge.
• These can be further divided into various operations (machine cycles).
• The first step of executing any instruction is the Opcode fetch cycle.
• In this cycle, the microprocessor brings in the instructions Opcode from memory.
• To differentiate this machine cycle from the very similar memory read cycle, the control status signals are set as follows
• IO/M0, s0 and s1 are both 1.
• This machine cycle has four T-states.
• The 8085 uses the first 3 T-states to fetch the opcode.
• T4 is used to decode and execute it.
• It is also possible for an instruction to have 6 T-states in an opcode fetch machine cycle.
• The memory read machine cycle is exactly the same as the opcode fetch except
• It only has 3 T-states
• The s0 signal is set to 0 instead.
• To understand the memory read machine cycle, lets study the execution of the following instruction
• In memory, this instruction looks like
• The first byte 3EH represents the opcode for loading a byte into the accumulator (MVI A), the second byte is the data to be loaded.
• The 8085 needs to read these two bytes from memory before it can execute the instruction. Therefore, it will need at least two machine cycles.
• The first machine cycle is the opcode fetch discussed earlier.
• The second machine cycle is the Memory Read Cycle.
• Figure 3.10 page 83.
• Machine cycles and instruction length, do not have a direct relationship.
• To illustrate lets look at the machine cycles needed to execute the following instruction.
• This is a 3-byte instruction requiring 4 machine cycles and 13 T-states.
• The machine code will be stored in memory as shown to the right
• This instruction requires the following 4 machine cycles
• Opcode fetch to fetch the opcode (32H) from location 2010H, decode it and determine that 2 more bytes are needed (4 T-states).
• Memory read to read the low order byte of the address (65H) (3 T-states).
• Memory read to read the high order byte of the address (20H) (3 T-states).
• A memory write to write the contents of the accumulator into the memory location.
• In a memory write operation
• The 8085 places the address (2065H) on the address bus
• Identifies the operation as a memory write (IO/M0, s10, s01).
• Places the contents of the accumulator on the data bus and asserts the signal WR.
• During the last T-state, the contents of the data bus are saved into the memory location.
• There needs to be a lot of interaction between the microprocessor and the memory for the exchange of information during program execution.
• Memory has its requirements on control signals and their timing.
• The microprocessor has its requirements as well.
• The interfacing operation is simply the matching of these requirements.
• The process of interfacing the above two chips is the same.
• However, the ROM does not have a WR signal.
• Accessing memory can be summarized into the following three steps
• Select the chip.
• Identify the memory register.
• Enable the appropriate buffer.
• Translating this to microprocessor domain
• The microprocessor places a 16-bit address on the address bus.
• Part of the address bus will select the chip and the other part will go through the address decoder to select the register.
• The signals IO/M and RD combined indicate that a memory read operation is in progress. The MEMR signal can be used to enable the RD line on the memory chip.
• The result of address decoding is the identification of a register for a given address.
• A large part of the address bus is usually connected directly to the address inputs of the memory chip.
• This portion is decoded internally within the chip.
• What concerns us is the other part that must be decoded externally to select the chip.
• This can be done either using logic gates or a decoder.
• Putting all of the concepts together, we get
• Data transfer operations
• Between registers
• Between memory location and a register
• Direct write to a register / memory
• Between I/O device and accumulator
• Arithmetic operations (ADD, SUB, INR, DCR)
• Logic operations
• Branching operations (JMP, CALL, RET)
• MOV B,A 47 From ACC to REG
• MOV C,D 4A Between two REGs
• MVI D,47 16 Direct-write into REGD 47
• Contents of ACC sent to output port number 05.
• Use a register PAIR as an address pointer !
• We can define memory access operations using the memory location (16 bit address) stored in a register pair BC, DE or HL.
• First, we have be able to load the register pairs.
• LXI B, (16-bit address)
• LXI D, (16-bit address)
• LXI H, (16-bit address)
• We can also increment / decrement register pairs.
• In many real-time operations, the microprocessor should be able to receive an external asynchronous signal (interrupt) while it is running a routine.
• When the interrupt signal arrives
• The processor will break its routine
• Go to a different routine (service routine)
• Complete the service routine
• Go back to the regular routine
• In order to execute an interrupt routine, the processor
• Should be able to accept interrupts (interrupt enable)
• Save the last content of the program counter (PC)
• Know where to go in program memory to execute
• the service routine
• Tell the outside world that it is executing an interrupt
• Go back to the saved PC location when finished.
• There are four other interrupt inputs in 8085 that
• transfer the operation immediately to a specific address
• TRAP go to 0024
• RST 7.5 go to 003C
• RST 6.5 0034
• RST 5.5 002C
• RST 7.5, RST 6.5 and RST 5.5 are maskable interrupts, they are acknowledged only if they are not masked !

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