• All Research Labs
  • 3D Deep Learning
  • Applied Research
  • Autonomous Vehicles
  • Deep Imagination
  • New and Featured
  • AI Art Gallery
  • AI & Machine Learning
  • Computer Vision
  • Academic Collaborations
  • Government Collaborations
  • Graduate Fellowship
  • Internships
  • Research Openings
  • Research Scientists
  • Meet the Team

Research Areas

Circuits and vlsi design, associated publications, researchers.

Search form

illustration of chip

Robust Low Power VLSI

Search This Site

  • Body Sensor Networks
  • Energy Efficient Circuit Design
  • Energy Harvesting and Power Management Unit
  • System-on-Chip
  • Design Automation
  • Wake-Up Receiver
  • Chip Gallery
  • Photo Gallery

The Robust Low Power VLSI Group, led by Professor Ben Calhoun, investigates research topics related to modern VLSI design. Among the many challenges facing circuit designers in deep sub-micron technologies, power and variation are perhaps the most critical. Our group's focus is to confront these problems in a range of applications and different regions of the design space. Our specific research interests include low power digital circuit design, sub-threshold digital circuits, SRAM design for end-of-the-roadmap silicon, variation tolerant circuit design methodologies, and medical applications for low energy electronics. The group is engaged in projects related to each of these topics.

Featured Projects

View more projects

In this project, a low power wireless ECG sensor is implemented using commercial off the shelf (COTS) components. The resulting system can acquire and process ECG data and send it wirelessly to a basestation such as a handheld device. The picture shows the ECG sensor in operation, with the PDA plotting the real time ECG signal.

research projects in vlsi

This work explores reconfigurable circuits operating at low voltages. While the existing FPGAs are too high power to meet the requirements of IoT applications, we designed and optimized new circuit typologies of CLBs and global interconnect in near/sun-threshold region. We also developed custom tool flow to support full chip configuration. A 90nm chip implements the FPGA with 1134 LUTs, which is 2.7X smaller, 14X faster, and 4.7X less energy than a sub-threshold FPGA using conventional circuits and 22X less energy than an equivalent FPGA at full VDD. We are currently working towards dynamic voltage scaling and measurements using real-life applications.

The artificial seal whisker project is a joint effort with the University of Virginia’s Mechanical Engineering Department and the University of California Santa Cruz to detect and track underwater wakes using an array of bio-inspired sensors. Previous biological work found harbor seals are able to track wakes using only their whiskers. In this project, the seal whisker team is focused on understanding how seals sense wakes using their whiskers, designing a capacitance based whisker-like sensor, and designing the electrical backend printed circuit board for sensing, storing, and transmitting data. The biologically inspired sensor’s design is based on seal whiskers and previous effort in the field involving spider hairs and fish lateral lines. All components will be integrated in the Wake Information Detection and Tracking System (WIDTS) to be carried by a trained harbor seal for testing.

Featured Chips

View more chips in the Chip Gallery

research projects in vlsi

The IEEE Circuits and Systems Society is the leading organization that promotes the advancement of the theory, analysis, computer-aided design and practical implementation of circuits, and the application of circuit theoretic techniques to systems and signal processing. The Society brings engineers, researchers, scientists and others involved in circuits and systems applications access to the industry’s most essential technical information, networking opportunities, career development tools, and many other exclusive benefits. 

More Information

Visit CASS MiLe

CASS MiLe Logo

The IEEE International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premiere forum for researchers in the active fields of theory, design and implementation of circuits and systems. This is accomplished through technical conference sessions, poster sessions, live demonstration sessions, and publication of conference papers. ISCAS 2024 is inspired by the theme "circuits and systems for sustainable development", which is perfectly aligned with the host city's goal.

Quantum Synergy: Advancing Computing Through Academic-Industry Collaboration

37th symposium on integrated circuits and systems design, 2024 ieee 37th international system-on-chip conference.

TVLSI-Cover

IEEE Transactions on Very Large Scale Integration Systems

Publication menu.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  covers design and realization of microelectronic systems using VLSI/ULSI technologies that require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.

To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded. The editorial board, consisting of international experts, invites original papers which emphasize the novel system integration aspects of microelectronic systems, including interactions among system design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and system level qualification. Thus, the coverage of this Transactions focuses on VLSI/ULSI microelectronic system integration.

Topics of special interest include, but are not strictly limited to, the following:

  • System Specification, Design and Partitioning
  • System-level Test
  • Reliable VLSI/ULSI Systems
  • High Performance Computing and Communication Systems
  • Wafer Scale Integration and Multichip Modules (MCMs)
  • High-Speed Interconnects in Microelectronic Systems
  • VLSI/ULSI Neural Networks and Their Applications
  • Adaptive Computing Systems with FPGA components
  • Mixed Analog/Digital Systems
  • Cost, Performance Tradeoffs of VLSI/ULSI Systems
  • Adaptive Computing Using Reconfigurable Components (FPGAs) 

The articles in this journal are peer reviewed in accordance with the requirements set forth in the  IEEE PSPB Operations Manual   (sections 8.2.1.C & 8.2.2.A). Each published article was reviewed by a minimum of two independent reviewers using a single-blind peer review process, where the identities of the reviewers are not known to the authors, but the reviewers know the identities of the authors. Articles will be screened for plagiarism before acceptance.

Corresponding authors from low-income countries are eligible for  waived or reduced open access APCs .

This publication considers original works that enhance the existing body of knowledge. Results described in the article should not have been submitted or published elsewhere. Expanded versions of conference publications may be submitted. Articles must be intelligible and must be written in standard English.

  • Peer Review : Peer review is vital to the quality of published research. Each article submitted to IEEE is evaluated by at least two independent reviewers selected by a member of the publication's editorial board.  Learn more about the IEEE peer review process .
  • Publication Fees : This publication is supported by subscriptions and applicable Article Processing Charges (APCs). Although there is no cost for publishing with IEEE, authors may wish to take advantage of some of our fee-based offerings; visit the  IEEE Author Center  for more information on available options.
  • Errors in Published Articles : Authors who have detected an error in their published article should contact the Editor-in-Chief shown above to request the publication of a correction. Note that no change may be made to the original article after it is published in IEEE  Xplore . Comment or Letter to the Editor articles which discuss an article in this publication will be considered. The authors of the original article will be given the opportunity to reply to the Comment or Letter to the Editor. Submit your Comment or Letter to the Editor article via Submit Manuscript above.

Other Policies

  • Publishing Ethics
  • Copyright and Licensing
  • Post-Publication Information
  • Advertising

Submit a Manuscript

Facebook    LinkedIn

IEEE Transactions on Very Large Scale Integration Systems (TVLSI) Editorial Board

Editor-in-chief, mircea r. stan, associate editor-in-chief, associate editor tvlsi, magdy abadir, tughrul arslan, amine bermak, chye chirin boon, andreas burg, chip hong chang, meng-fan (marvin) chang, yao-wen chang, yong (nick) chen, paolo s. crovetti, josé pineda de gyvez, raffaele de rose, shiro dosho, rolf drechsler, ibrahim (abe) elfadel, xuanyao (kelvin) fong, masanori hashimoto, deukhyoun heo, tsung-yi ho, houman homayoun, yuh-shyan hwang, rajiv joshi, tanay karnik, tony tae-hyoung kim, chulwoo kim, seok-bum ko, jaydeep kulkarni, volkan kursun, yoonmyung lee, hai (helen) li, longyang lin, prabhat mishra, baker mohammad, mehran mozaffari kermani, makoto nagata, mahdi nikdast, partha p pande, bipul c. paul, vasilis pavlidis, khaled n salama, patrick schaumont, fabio sebastiano, anirban sengupta, mingoo seok, vaishnav srinivas, ioannis l. syllaios, armin tajalli, mark tehranipoor, aida todri-sanial, marian verhelst, valerio vignoli, xiaoqing wen, kaiyuan yang, zhengya zhang, mark zwolinski, editorial assistant, stacey weber jackson.

research projects in vlsi

VLSI-SoC: Design Trends

28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6–9, 2020, Revised and Extended Selected Papers

  • Conference proceedings
  • © 2021
  • Andrea Calimera   ORCID: https://orcid.org/0000-0001-5881-3811 0 ,
  • Pierre-Emmanuel Gaillardon   ORCID: https://orcid.org/0000-0003-3634-3999 1 ,
  • Kunal Korgaonkar   ORCID: https://orcid.org/0000-0002-9078-2944 2 ,
  • Shahar Kvatinsky   ORCID: https://orcid.org/0000-0001-7277-7271 3 ,
  • Ricardo Reis   ORCID: https://orcid.org/0000-0001-5781-5858 4

Politecnico di Torino, Turin, Italy

You can also search for this editor in PubMed   Google Scholar

University of Utah, Salt Lake City, USA

Technion – israel institute of technology, haifa, israel, universidade federal do rio grande do sul, porto alegre, brazil.

Part of the book series: IFIP Advances in Information and Communication Technology (IFIPAICT, volume 621)

Included in the following conference series:

  • VLSI-SoC: IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip

Conference proceedings info: VLSI-SoC 2020.

19k Accesses

11 Citations

6 Altmetric

This is a preview of subscription content, log in via an institution to check access.

Access this book

Subscribe and save.

  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
  • Durable hardcover edition

Tax calculation will be finalised at checkout

Other ways to access

Licence this eBook for your library

Institutional subscriptions

About this book

The 16 full papers included in this volume were carefully reviewed and selected from the 38 papers (out of 74 submissions) presented at the conference. The papers discuss the latest academic and industrial results and developments as well as future trends in the field of System-on-Chip (SoC) design, considering the challenges of nano-scale, state-of-the-art and emerging manufacturing technologies. In particular they address cutting-edge research fields like low-power design of RF, analog and mixed-signal circuits, EDA tools for the synthesis and verification of heterogenous SoCs, accelerators for cryptography and deep learning and on-chip Interconnection system, reliability and testing, and integration of 3D-ICs.

*The conference was held virtually.

Similar content being viewed by others

research projects in vlsi

Very Large Scale Integration (VLSI) and ASICs

research projects in vlsi

VLSI-SoC: An Enduring Tradition

research projects in vlsi

ITRS 2028—International Roadmap of Semiconductors

  • artificial intelligence
  • communication systems
  • computer hardware
  • computer-aided design
  • distributed computer systems
  • distributed systems
  • embedded systems
  • field programmable gate array
  • integrated circuits
  • microprocessor chips
  • network protocols
  • parallel processing systems
  • signal processing
  • telecommunication systems
  • vlsi circuits

Table of contents (16 papers)

Front matter, low-power high-speed adcs for adc-based wireline receivers in 22 nm fdsoi.

  • David Cordova, Wim Cops, Yann Deval, François Rivet, Herve Lapuyade, Nicolas Nodenot et al.

Mixed-Mode Signal Processing for Implementing MCMC MIMO Detector

  • Amin Aghighi, Behrouz Farhang-Boroujeny, Armin Tajalli

Low Power Current-Mode Relaxation Oscillators for Temperature and Supply Voltage Monitoring

  • Shanshan Dai, Caleb R. Tulloss, Xiaoyu Lian, Kangping Hu, Sherief Reda, Jacob K. Rosenstein

Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation

  • Tutu Ajayi, Sumanth Kamineni, Morteza Fayazi, Yaswanth K. Cherivirala, Kyumin Kwon, Shourya Gupta et al.

Assessing the Configuration Space of the Open Source NVDLA Deep Learning Accelerator on a Mainstream MPSoC Platform

  • Alessandro Veronesi, Davide Bertozzi, Milos Krstic

SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays

  • Yukio Miyasaka, Masahiro Fujita, Alan Mishchenko, John Wawrzynek

Learning Based Timing Closure on Relative Timed Design

  • Tannu Sharma, Sumanth Kolluru, Kenneth S. Stevens

Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication

  • Rakshith Saligram, Ankit Kaul, Muhannad S. Bakir, Arijit Raychowdhury

From Informal Specifications to an ABV Framework for Industrial Firmware Verification

  • Samuele Germiniani, Moreno Bragaglio, Graziano Pravadelli

Modular Functional Testing: Targeting the Small Embedded Memories in GPUs

  • Josie Esteban Rodriguez Condia, Matteo Sonza Reorda

RAT: A Lightweight Architecture Independent System-Level Soft Error Mitigation Technique

  • Jonas Gava, Ricardo Reis, Luciano Ost

SANSCrypt: Sporadic-Authentication-Based Sequential Logic Encryption

  • Yinghua Hu, Kaixin Yang, Shahin Nazarian, Pierluigi Nuzzo

3D Nanofabric : Layout Challenges and Solutions for Ultra-scaled Logic Designs

  • Edouard Giacomin, Juergen Boemmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon

3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model

  • Arnaud Poittevin, Chhandak Mukherjee, Ian O’Connor, Cristell Maneux, Guilhem Larrieu, Marina Deng et al.

Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics

  • Brian Crafton, Samuel Spetalnick, Gauthaman Murali, Tushar Krishna, Sung-Kyu Lim, Arijit Raychowdhury

abstractPIM: A Technology Backward-Compatible Compilation Flow for Processing-In-Memory

  • Adi Eliahu, Rotem Ben-Hur, Ronny Ronen, Shahar Kvatinsky

Back Matter

Other volumes, editors and affiliations.

Andrea Calimera

Pierre-Emmanuel Gaillardon

Kunal Korgaonkar, Shahar Kvatinsky

Ricardo Reis

Bibliographic Information

Book Title : VLSI-SoC: Design Trends

Book Subtitle : 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6–9, 2020, Revised and Extended Selected Papers

Editors : Andrea Calimera, Pierre-Emmanuel Gaillardon, Kunal Korgaonkar, Shahar Kvatinsky, Ricardo Reis

Series Title : IFIP Advances in Information and Communication Technology

DOI : https://doi.org/10.1007/978-3-030-81641-4

Publisher : Springer Cham

eBook Packages : Computer Science , Computer Science (R0)

Copyright Information : IFIP International Federation for Information Processing 2021

Hardcover ISBN : 978-3-030-81640-7 Published: 15 July 2021

Softcover ISBN : 978-3-030-81643-8 Published: 15 July 2022

eBook ISBN : 978-3-030-81641-4 Published: 14 July 2021

Series ISSN : 1868-4238

Series E-ISSN : 1868-422X

Edition Number : 1

Number of Pages : XVIII, 364

Number of Illustrations : 70 b/w illustrations, 139 illustrations in colour

Topics : Computer Systems Organization and Communication Networks , Control Structures and Microprogramming , Input/Output and Data Communications , Information Systems Applications (incl. Internet)

  • Publish with us

Policies and ethics

Societies and partnerships

The International Federation for Information Processing

  • Find a journal
  • Track your research

WatElectronics.com

VLSI Projects for Engineering Students

October 9, 2021 By WatElectronics

Very Large Scale Integration Technology (VLSI) is an IC technology, designed by integrating a large number of electronic components such as logic gates , transistors , FET’s , etc. This technology mainly focuses on three major design and physical constraints related to an electric circuit like power, area, and speed. Some of the important VLSI Projects are mentioned below. A few of the VLSI platforms that are currently upcoming are FPGA applications, SOCs, and ASIC designs.

The list of VLSI Projects using wireless, sensors, home automation, Xilinx, Mathlab, SOC, Bluetooth & other projects are discussed below. These projects are very helpful for beginners, diploma students, and engineering students.

VLSI Projects using Verilog

Verilog is one of the software languages used in VLSI technology for defining electronic circuits and their system of design. It represents the electronic circuit design by simulating the program line of code, for representing analysis of test result in terms of positive or negative and also syntheses logic.

VLSI Projects using Verilog

The list of VLSI projects based on Verilog code includes the following.

1). Design of Low Power and Enhance Speed Multiplier and Accumulator With SPST Adder in Verilog

The performance of an electronic device depends mainly on power and device heating. The aim of this project is to minimize power factors and improve the speed of MAC using the Spurious Power Suppression Technique over a modified version of the Booth type encoder .

2). Design of Hamming Type Code using FPGA in Verilog

The aim of this project is to design hardware for implementing Hamming based code for encoder and decoder systems over wireless communication . It uses FPGA on which code written in VHDL of Xilinx is executed.

3). Gabor Type Filter for Biometric Recognition with Verilog HDL

The aim of this project is to design a smart biometric fingerprinting system using Gabor filter on the VLSI project  platform. This project is coded grayscale filter which is a part of Gabor filter design in VHDL language and executed on FPGA .

4). Enhanced Speed and Minimum Complexity Design of a Reed Solomon Type Decoder

The aim of this project is to design a simple Reed Solomon type decoder using VLSI technology. This project uses the Berlekamp Massey type algorithm , which is programmed in Verilog HDL. Reed Solomon decoder provides enhance speed.

5). Design and Implementing Vending Machine in Verilog HDL

The aim of this project is to design a vending machine using VLSI technology . The designed machine is programmed in VHDL and dumped on FPGA that gives speed response than microcontroller type VM.

VLSI Projects using Xilinx Software

Xilinx Integrated Synthesis Environment is a tool designed for analyzing HDL and synthesizing Xilinx. Its purpose is to develop embedded based firmware for the Xilinx class of CPLD and FPGA IC technology products. They aid developers to compile circuit designs and allow the configuration of the target devices.

VLSI Projects Using Xilinx Software

VLSI Projects Using Xilinx Software

The list of VLSI projects based on Xilinx software includes the following.

1). Design of TIC TAC TOE Game on Spartan3 Type FPGA using Image Processing

The aim of this project is to design a fun game board called Tic Tac Toe for two players using VHDL. It uses a screen board, LED bulbs, wires, FPGA, sensors , and wires. programmed playing board and FPGA need to be interfaced with the playing board using Xilinx.

2). BPSK Type Implementation on Xilinx System Generator using Spartan3 FPGA Image Processing Kit

The aim of this project is to design BPSK keying modulation type and demodulation type using the Matlab platform. Components used in this project are, FPGA, Matlab, multiplexers , filters such as FIR, and comparators . It is designed on Matlab and generated on SPARTAN.

3). Design QPSK And Synthesizing Its Result

The aim of this project is to design and implement QPSK modulation for satellite based radio applications. This project designs QPSK logic using reverse gate logic executed on Xilinx with VHDL code.

4). Implementation of Bus Based Bridge for Connecting AHB and OCP Bus

The aim of this project is to design a communication bus to connect the other two busses on SOC applications. Components used in this project are SOC, AHB bus, OCP ( Open Core Protocol) bus, and software Xilinx.

5). Design of a Live Traffic Light Based Control System using Xilinx

The aim of this project is to design and implement VLSI code on FPGA for traffic light signals. Components used in this project are FPGA, LED bulbs red, yellow, and green; software Xilinx. The code in this project is written in VHDL

6). Design of OFDM System using IFFT and FFT Transfer Functions

The aim of this project is to design an OFDM system employing FFT and Inverse FFT signal processing on the VLSI platform. This project is written in VHDL coding language and simulated on Xilinx.

7). Floating Point Based Fused Addition, Subtraction, and Fused Dot type Product Units Design

The aim of this project is to design and simulate the parallel operation of floating point type add, subtract, and multiplication type operation using floating type point add, multiplication, and subtract dot product based units in parallel on Xilinx.

8). FPGA Based Mutual Authentication Type Protocol with Modular Arithmetic

Security systems are designed in a smart way they provide access only to authenticators. The aim of this project is to design a higher enhanced protocol for security applications like RFID tags and readers using the VLSI platform programmed in VHDL and simulated on Xilinx.

VLSI Projects using VHDL

A Hardware Description Language (VHDL) is a software program for Very High Speed Integrated Circuit (VHSIC). The purpose of this language is to define the functioning of electronic components on designed circuitry. This language was designed by IEEE and containing VHDL 1987 and 1993 versions for the design of hardware and developing test entities in order to verify hardware behavior.

The list of VLSI projects based on VHDL code includes the following.

1). VGA Type Bouncing Ball Interfacing with Spartan3 Type FPGA for Image Processing Kit

The aim of this project is to design a smart system for VGA on VLSI technology. It uses VGA, bouncing ball, Spartan 3 type FPGA, and connecting wires. The designed hardware programmed using VHDL provides an efficient system with multiple screen pixel display up to WXGA 1280 by 800.

2). Generating PWM Type Signal With Variable Type Duty Cycle on FPGA

The aim of this project is to design and implement a voltage controller PWM using FPGA. Components used in this project are FPGA, PWM signal generator , and software platform VHDL. This system generates a higher value of frequency at the dynamic duty cycle.

3). Implementation of Digital Type Clock with Spartan3an Type FPGA Evaluation Kit

The aim of this project is to design a smart digital clock using VLSI technology. Components used in this project are FPGA, crystal, programming platform VHDL, 2 by 16 LCD, and 50 Hz clock generating circuit. The advantage of this clock is it is portable and displays accurate values.

4). Design of AMBA with AHB BUS Compliant Type Memory Controller

The aim of this project is to design a controller system for controlling CPUs memory containing Read Only Memory and Static Random Access Memory on an AMBA BUS using VLSI technology. This project uses VHDL software for synthesizing results.

5). Design of FPGA based 32-bit Floating Type Point Arithmetic Unit

The aim of this project is to design and implement a floating point number using an arithmetic unit on the VLSI platform. The components used in this technology are FPGA, ALU unit, software code written in VHDL, and also simulated using MAT Lab.

6). Design of a Field Programmable Type CRC Circuit Architecture and Synthesize Architectural Result

The aim of this project is to design and implement a Cyclic type Redundancy Check (CRC) computation circuit using VLSI technology. This project obtains multiple serial processing cells using the matrix method. The components used are FPGA, CRC circuit, and VHDL code.

VLSI Projects using MatLab

Matlab is a software tool designed for performing mathematical and logic calculations such as differentiation, Laplace transform, differential equation, inverse functions, etc. The main purpose of Matlab along with VLSI is to provide solutions for electronic circuits using a causal model type approach.

VLSI Projects using MatLab

The list of VLSI projects based on Matlab code includes the following.

1). Design of Fuzzy Type Logic for a Mobile Robot Controller with VHDL

The aim of this project is to design and program a robot using VLSI technology. This robot is programmed to move objects using fuzzy logic on MATLAB software and later translated into VHDL before implementing on hardware.

2). VLSI Implementation of DWT for Image Compression using VLSI

The aim of this project is to design a discrete type wavelet transform (DWT) algorithm using the VLSI platform for image processing type applications. In this project, code is written simulated, and implemented in VHDL and MATLAB.

List of Other VLSI Projects

The list of other VLSI projects includes the following.

1). 3D Technology Based Lifting of Discrete Wavelet Transform (DWT)

The aim of this project is to design an assistant system for high quality image generation system using VLSI technology. It uses a 3D based lifting type filter to generate a discrete wavelet using the VLSI programming language; the advantage is no loss of image quality is observed.

2). Design of Enhance Speed for Hardware Efficient 4-Bit SFQ Type Multiplier

The aim of this VLSI project is to design an advanced version of the conventional type booth encoder. This encoder is designed with a 4-bit SFQ (Single Flux Quantum) multiplier, that provides an enhanced speed and performance for critical type delay applications.

3). Design of Universal Based Cryptography Processor Employed in Smart Cards

The aim of this project is to design a smart universal cryptoprocessor for a card system. This project is designed with the public & private keys using a combination of 3 Data Encryption Standard (DES), Advanced Encryption Standard (AES), and Elliptic Curve Cryptography (ECC).

Design of Universal Based Cryptography Processor Employed in Smart Cards

Design of Universal Based Cryptography Processor Employed in Smart Cards

4). Design of An Enhanced Speed and Minimum Power Multiplier with Spurious Type Power Suppression Technique (SPST)

The aim of this project is to design a system to remove spurious signals from the arithmetic unit using a spurious power type suppression method. A multiplier component operating at a greater velocity consumes less power during data communication with the target location.

5). Design of A Lossless Based Data Compression and Decompression Method and Its Hardware Architecture

The aim of this project is to design an architecture for a 2 stage hardware using an Adaptive Huffman algorithm and Parallel dictionary type LZW algorithm (PDLZW). This project mainly focuses on lossless data decompression and compression applications.

6). Design of Minimum Complexity Turbo Type Decoder Architecture Employed in Energy-Efficient Wireless Sensor Networks

The aim of this project is to design a smart power conservation system during wireless communication over a WSN network. This minimizes the power of the LUT type Log BCJJR type algorithm during communication over WSN into a fundamental ADD Compare Select operation.

7). Design of Optimal VLSI Based Architecture to Filter Impulse Type Noise in Image

The aim of this project is to design a noise filtering system for an image processing application. This project is implemented on a VLSI architecture with an edge type preserving filter. This project benefits in terms of image quality.

8). Design of Processor In Type Memory Architecture for Image and Video Compression System

The aim of this project is to design a system with minimum complex processor-in & a memory architecture to aid multimedia applications for compressing the size on applying instructions in a word, one instruction, and other image and video-related data concepts.

9). Design of Symbol Type Rate Timing Synchronization Procedure for Minimum Power Wireless OFDM Systems

The aim of this project is to design a performance enhancing system for a wireless type OFDM system. This method achieves less power consumption via a dynamic type sample timing type controller and a tunable type clock based generator.

10). Bluetooth Technology Based Wireless Type Home Automation System

The aim of this project is to program an FPGA to control home appliances using a mobile phone. Components used in this project are Field Programmable Gate Array (FPGA), lights sensors, and mobile phones. It saves electric power and provides remote users access via mobile.

11). Design of Automation ARM Controller on FPGA

The aim of this project is to design an arm that is controlled using FPGA. It uses Spartab3an, FPGA, mechanical arm, objects, and connectors. FPGA is programmed to move the robot arm and pic the objects. Such kind of robotic arm project is suitable for industrial repetitive tasks.

12). Cloud Technology Based Temperature Monitoring System

The aim of this project is to design a smart temperature monitoring system using VLSI technology. It uses Spartan3an FPGA, Wi-Fi technology, and internet cloud services. Spartan3an broadcast the live temperature status over the internet and stockpiles the data over the cloud.

13). Design of Multiple Channel for UART on FPGA

The aim of this project is to design a multi type channel UART based controller depending on the asynchronous FIFO method with FPGA for scaling and re-configuring the communicating device when required. It uses FPGA Spartan3an and a complex type communication system.

14). Design of Linear Type and Morphological Type Image Filtering with FPGA Image Processing Kit

The aim of the project is to use real-time algorithms such as 2D type morphological and convolution based filters for showcasing image processes for multiple applications. It uses Spartan3 type FPGA, VLSI technology, an image processing module, and connecting wires.

15). Design of PGA Implementation for Distance Measurement using Ultrasonic Sensor on FPGA

Aim of this project is to design smart distance object tracking systems using VLSI technology. It uses an ultrasonic type sensor, Spartan 3FPGA board, a display system, and an alarm. The automation system tracks object and sends to Spartan3 which and displays on the screen.

16). Design of Booth Type Multiplier on Spartan6 FPGA Board

The aim of this project is to design an enhanced version of a multiplier to improve the performance of digital signal processors in terms of speed and area. Components used in this project are Multiplier & Accumulator of Radix 4, Booth type multiplier algorithm, Spartan6 FPGA, and DSP processor.

17). Lifting Type Discrete Wavelet Transform (DWT) on Spartan3 FPGA with Image Processing Kit

The aim of this project is to design lifting type Discrete based Wavelet Transform for discarding Finite Impulsive type Response with finite based continuous filtering steps. This project is implemented on 1 D and 2D technology.

18). Design of Tetrix Type Game on Spartan3 FPGA with Image Processing Kit

The aim of this project is to design an object detection system using FPGA. It uses a space communication system, antenna, Spartan 3, and display system. This system detects if there is any object in the direction of the antenna and shifts the angle in direction of obstacle free.

19). Design of Medical Based Image Fusion on Spartan 3 Type FPGA

The aim of this project is to design a smart image generation system for medical purposes using MAT LAB. This replaces MRI and CT scanning medical device that generates images with noise and disturbances. It uses Spartan3 FPGA, VB software, MAT Lab, and XPS software.

20). Design of Median Type Filter Implementation on Spartan3 Type FPGA with Image Processing Kit

The aim of this project is to design a system to eliminate noise from the image processing system. Components used in this project are median filter, Spartan 3 FPGA, processor kit for image, and a software name 3 by 3 sliding window algorithm .

21). Design of Sobal Edge Detection using Spartan3 Type FPGA

The aim of this project is to design a Sobel edge type detection algorithm for detecting image pixels within a second. Components used in this project are FPGA XC3S200 – 4tq144, Sobel algorithm, Matlab platform, and display system. This system processes 128 by 128 by 8 pixels of grayscale based images.

22). FPGA Implementation of Keyboard Learner using Spartan3 FPGA Image processing Kit

The aim of this project is to design a smart keyboard system using VLSI technology. In this user mainly focus on the screen rather than the keyboard that is when a user types half a word the software displays nearby keywords on the screen and automatically updates the full word based on the movement of the user’s eyes on the screen.

23). Design of PIR Type Security Alert System on Spartan 3an Based FPGA Starter Kit

The aim of this project is to design a smart security system using VLSI technology. The components used in this project are a PIR sensor that detects the motion of a nearby object in a restricted zone, a camera, an FPGA module “Spartan 3”, and a screen. This project allows access entry only to a legitimate user.

24). Design of AES Encryption Algorithm on Spartan6 Type FPGA

The aim of this project is to design highly secure communication over the internet using AES on the VLSI platform. The components used in this project are Spartan 6 FPGA, software platform VHDL, and AES algorithm. The advantage of this project is it provides high security and consumes less power.

25). Design of Wireless Type Temperature Monitoring System using Spartan3an Type FPGA on Starter Kit for Agriculture Application

The aim of this project is to design a temperature monitoring system for agriculture using VLSI technology. The components used in this project are a temperature sensor, FPGA kit, programming platform VHDL, and agriculture land.

26). Design of Enhance Throughput Based VLSI Architecture for Blackman Windowing in Real Time Spectral Analysis

The aim of this project is to design a smart system to generate maximum throughput on the VLSI platform. This project uses Black man windowing instead of using processors such as DSP or ROM. This project is designed using the VHDL programming language.

27). Approximate Based Search CAM for DNA Sequencing and Genome Analysis

The aim of this project is to design and implement a smart system that detects COVID mutant through COVID affected person DNA on VLSI technology. Components used in this project are the VHDL programming platform, DNA sample from a patient, FPGA, and report tracking system.

28). Design of Hardware for Video Type Processing Superblock Based Accelerator

The aim of this project is to design a high speed video processor for real-time based video stream. This system undergoes three stages namely Alpha blending, polynomial transformation, and low pass filtering. The advantage of this project is it provides noise free video quality.

29). Design of Collision Less Robot Processor on VLSI and RFID Technology

The aim of this project is to design an algorithm for aiding robots to walk without colliding with other robots or obstacles in their environment on VLSI technology. Components used in this technology are RFID reader and RFID card, VHDL, processor, and objects.

30). Design of Adiabatic Based Technique for Power-Efficient Logic Circuit Design

A CMOS circuit is built with multiple gates such as NOR and NAND combinations but these circuits have higher power consumption faction. The aim of this project is to replace the CMOS circuit and design advance enhanced logic type circuits using the adiabatic type technique for minimizing and reusing power.

31). Design of Advanced Encryption System (AES) for Improving System Computing Speed

AES provides high encryption of data over digital communication. The aim of this project is to design and implement an AES encryption algorithm on an FPGA board and simulate it in VHDL software. The advantage of this project is it enhances the encryption factor with high-speed communication.

32). Design of AMBA with Advanced High-Performance Bus (AHB) with IP Block

The aim of this project is to design Advanced Microcontroller Bus Architecture (AMBA) with additional bus AHB using VLSI technology. This project is implemented with slave–master modules. Where master is programmed to control their slave’s components.

33). A Multichannel with Multimode RF Type Transceiver using DSM

The aim of this project is to implement RF type multi-channel emitter and collector working in multi-mode via delta type sigma modulator. Components used in this project are VHDL, Delta Sigma type modulator, and RF channel with communicating components.

34). Asynchronous Type Transfer Mode Based Knockout Switch Concentrator

The aim of this project is to design and implement a networking class switch for datagram and virtual type circuit packet network on VLSI technology. Components used are concentrator of asynchronous type transfers knockout switch , the software platform on VHDL and FPGA.

35). Design of Behavioral Synthesis for Asynchronous Type Circuits

The aim of this project is to design and implement asynchronous type circuits and balsa module templates using the VLSI platform. This project synthesis circuit results in behavioral mode.

36). Implementation of Carrying Type Tree Adder

The aim of this project is to design enhance versions of adders such as parallel prefix adders using VLSI technology to minimize power. This project also synthesizes types of carrying tree adders such as sparse kogge-stone, spanning type tree, and kogge type stone adder.

37). Fixed Angle of Rotation using CORDIC Designs

The aim of this project is to design and implement rotating vectors on coordinate rotation type digital based computer method via at stationary and using reference angles. This project is used in applications like image processing, games, and robotics.

38). Design of an SOC Based Permutation Network on a Multiprocessor

The aim of this project is to control traffic on multiprocessor SOC based applications using VLSI technology. This project is mainly designed for real time based applications for providing enhanced device performance of IP communication.

39). Design of VLSI Based Architecture for Visible Type Watermarking on Secure Still Digital Camera (S2DC) Design

The aim of this project is to design and implement a smart chip for a digital camera using VLSI technology. The purpose of this chip in a digital camera is to develop watermarking on images. Components used are the S2DC camera, chip, and VHDL software.

40). Design of Efficient Systolic Type Array Architecture on VLSI

The aim of this project is to design and implement a systolic type array multiplier using the VLSI platform. This designed multiplier can be further used as a binary multiplier to compute binary type multiplications. Components used are FPGA and code written in VHDL.

41). Design of Multi Type Value Logic With Quantum Dot Gate Type FET

The aim of this project is to design and implement a smart 3 stages quantum Dot based Gate FET circuit to handle an increase in a logic bit in logic circuits. This project is used in applications such as decoders and Op-Amps .

42). Design of FFT Type Processor Using Radix-4 Algorithm on FPGA

The aim of this project is to design and synthesize processors for Orthogonal Frequency type Division Multiplexer (OFDM) and wireless LAN networks in the VLSI platform. This project synthesize a 256 point FFT type processor of Radix 4 in VHDL coding language.

43). Design of 32 Â bit type RISC Processor using VLSI

The aim of this project is to design a 32 bit RISC based architecture on the VLSI platform. This project divides into 16 sets of instructions and executes every instruction in a single cycle with a 5 stage parallel execution method.

44). Design of VHDL Based Model for a Smart Sensor System

A sensor is a device that senses the physical parameter within its environment. The aim of this project is to design a program for a sensor for canceling the noise generated from the sensor on the VLSI platform. This project is designed in the VHDL language.

45). Fuzzy Type PID Controller with VHDL for Transportation Application of OSI

The aim of this project is to design a smart anti-collision system for vehicles using Fuzzy logic on the VLSI platform. This project uses a PDI type controller with a cruise system to prevent accidents in vehicles. A fuzzy algorithm is developed using VHDL.

46). Design of Control Area Network Protocol on VLSI

The aim of this project is to design an Eight A to Eleven type modulation technique for a CAN protocol on the VLSI platform. This modulation technique overcomes the drawback of the conventional Software Bit Stuffing type technique. Software code in this project is written in VHDL.

47). Design of DMA Controller for AMBA Type Bus For IP Core

The aim of this project is to design a smart DMA controller for SOC based satellite applications using the VLSI platform. This project designs a DMA controller for satellite using VHDL code for faster and noise free communication.

48). Enhanced Precision Stepper Type Motor Controller Implementation on FPGA

The aim of this project is to design a controller for the stepper motor on the VLSI platform. The stepper motor on FPGA in this project is controlled on programming PWM technique using VHDL software language.

49). Modeling and Design of I2C Type Bus Controller

The aim of this is to mode the I2C bus on a VLSI software platform. Here in this project I2C wok on master and slave architecture. Where code is written in VHDL language to control master and slave.

50). Design of CPLD Type Solar Based Power Saving System

The aim of this project is to design a CPLD for street lights using solar energy and VLSI technology. In this project Complex, Programmable Logic Device (CPLD) traps sufficient solar energy and chargers the battery, and turns on the street light during night time.

51). Design of Digital Space Vector on PWM Three Phase Based Voltage Source Inverter on FPGA

The aim of this project is to design and implement code for a smart voltage type source inverter (VSI) using VLSI technology. Components used in this project are FPGA, VSI, DSVPWM controller of 3 phase, and motor driver. This project is designed using the VHDL software language.

52). Design of Performance-Based Evaluation for Complex Type Multiplier with Advance Algorithm

The aim of this project is to design a system for evaluating complex mathematic Vedic multiplier operations using the VLSI platform. In this project, a 4 bit type multiplication using both Vedic and booth algorithms are simulated in the VHDL language.

53). A Highly linear Type CMOS Gm-C Low Pass Filter in Mobile Communication

The aim of this project is to design an operational transconductance type amplifier (OTA) of the Butterworth filter. The advantage of this project is it provides a medium free communication receiver.

54). Design of High Throughput Based DCT Core Design with Efficient Computation Mechanism

The aim of this project is to design an efficient hardware for image compression type application using Discrete type cosine transform based algorithm on VLSI technology. Components used in this project are FPGA, image processor, image processor, and software coded in VHDL.

55). Design of Low Power Based QVCO with Adiabatic Logic

The aim of this project is to design a control system for minimizing power factor in quadrature based voltage type controlled oscillator using Adiabatic logic on the VLSI platform. Components used in this project are CMOS machine with 0.18 radio frequency, QVCO, FPGA, and program coded in VHDL.

56). Design of Low Power Type Adaptive Viterbi Decoder Design with Trellis Type Coded Modulation

The aim of this project is to design and implement a system to minimize corruption of data during data communication in channels that use modulation techniques using the Viterbi decoder algorithm and VLSI platform for trellis coded modulation.

57). Enhancement of the Orthogonal Based Code Convolution Capabilities on FPGA Implementation

The aim of this project is to design an error type detection system for data communication using VLSI technology. It uses FPGA for executing OCC in the VHDL programming language. This project overcomes limitations of 16 bit and 8 bit orthogonal type code.

58). Design of Non-Volatile Type Memory Based On Improved Writing Circuit using STT-MRAM Technique

The aim of this project is to design and implement spin based transfer torque with a Magnetic class of flip flop for non volatile memory such as STT- MRAM using VLSI technology. This project minimizes area occupied and power consumption compared to SRAM.

59). Address Remapping Technique using Arithmetic Functions and ROM Based Approximation Approaches

The aim of this project is to design a system for speed ROM access using VLSI technology. This can be possible by non uniformly partitioning and minimizing ROM size and later used for remapping. The code for this project is written in VHDL.

60). Design of Flip-Flops for Enhanced Performance VLSI Based Applications with Deep Submicron CMOS Technology

The aim of this project is to design an optimized power and high speed system for digital communication and components applications such as buffers and microprocessors. This project uses flip flops such as TSPC, C2CMOS, DET, and SET.

61). Design of Low Power Based H.264 Video Compression Type Architecture for Mobile Communication

The aim of this project is to design an optimized system for minimizing access to memory and cost of computation of variable type block size motion estimation (VBSME) through pixel truncation with maintain good picture quality and minimizing power consumption.

62). Design of Improved Scan Technique in Low Power Scan Testing

The aim of this project is to design an architecture for capturing the shift response of a flip flop using VLSI technology in less power. This project mainly focuses on capture and peak test power.

63). Design of Space-Based Exploration Field Type Programmable Counter

The aim of this project is to design a smart exploration system in terms of area for the FPGA controller. This project is programmed in VHDL and executed on Altera Stratix II FPGA Architecture. This project minimizes in terms of optimizing area for each component on FPGA.

64). Design of Power Gating Implementation for Noise Filtration with Body Tied Triple Well Structure

The aim of this project is to design a chip of 65 nm for removing disturbances with object tied structure in triple well using power type grating technique. The quality obtained from this project is 95 percent noise-free.

65). VHDL Based Universal Asynchronous Receiver Transmitter (UART)

The aim of this project is to design UART in VLSI technology for detecting errors and activating baud generation. This project detects errors in terms of overflow, stop, break, and parity error.

66). Design of 3GPP Based LTE Advance Turbo Encoder and Turbo Decoder with ASIC Implementation

The aim of this project is to design efficient architecture for 3GPP LTE of the Advance Turbo version of encoder and decoder on the VLSI platform. This architecture is implemented with a convolution type interleaved programmed in VHDL.

67). Design of Low Power Based Multiplier with Compound Constant Delay Logic Style

The aim of this project is to design a comparator system with an optimized power factor using VLSI technology. Designed systems facilitate comparison results between various multipliers such as Baugh Wooley, Wallace tree, and array . It is programmed in VHDL.

68). Design of Flash-Based ADC using Improved Comparator Scheme

The aim of this project is to overcome the drawback of power consumption in a traditional comparator. This project designs flash type ADC on the VLSI platform using a combination of MUX, comparator, and ladder resistor network.

69). Enhanced Performance-Based Flash Storage Type System Based on Virtual Memory and Write Buffer

The aim of this project is to improve the performance of flash storage while performing read and write operations. This project is written in VHDL code.

70). An Effective Type Leading Zero Anticipation for High Speed Floating Point Addition and Subtraction

The aim of this project is to design a Leading Zero Anticipation logic on the VLSI platform for providing enhance the speed of a floating-point subtraction and addition operation and addition operation. This project is used in DSP, CISC , RISC, and other microprocessor applications.

71). FPGA Based Implementation of an LFSR for Pseudorandom Pattern Generator for MEMS Testing

The aim of this project is to design an LFSR type pseudorandom type pattern generator using a mixed type mode bade modeling technique in a modular fashion in VLSI technology. This project programs code in VHDL and executes on FPGA.

72). Power Optimization of Linear Based Feedback Shift Register (LFSR) for Minimum Power BIST Implemented in HDL

The aim of this project is to design an LFSR for a Built-in self-test application, using the VLSI platform. The advantage of this project is it minimizes the amount of power consumed. This project is programmed using the VHDL language.

73). Design of FM Radio Receiver on Digital Type Demodulation

The aim of this project is to design a frequency modulation receiver using VLSI technology. This receiver is designed using a phase lock loop process, programmed in VHDL, and executed on an FPGA.

74). Implementation of Enhanced Speed Pipeline Based VLSI Architectures

The aim of this project is to efficient architecture that computes one and two dimensions discrete type wavelets using VLSI. This project benefits in terms of reducing speed, frequency of operation, and clock cycles.

75). Design of Phase, Frequency Detector, and Charge Pump for Enhanced Frequency PLL

The aim of this project is to design a charger and frequency type detector on VLSI technology. This project designs the detector and pump using the CMOS process used to enhance speed and less power consumed low jitter type applications.

76). Design of Cache Type Memory using Cache Based Controller on VHDL

The cache is a computer memory used for temporary storage and provides fast memory access. The aim of this project is to design a controller and detector system for tracking and identifying missed cache using the VLSI platform. This project is programmed using VHDL.

77). Design for Prepaid Based Electricity Billing System using SOC

The aim of this project is to design a smart electric power bill generator using the VLSI platform. This project is mainly implemented on ASIC and simulated in VHDL. This system automatically tracks the power consumed and generates bills per Watt’s consumption.

78). Enhanced Speed Network Based Devices Employed with SRL16 Reconfigurable Content Addressable Memory (RCAM)

The aim of this project is to design an SRL 16 type content based CAM unit using VLSI technology on FPGA. The advantage of this project is it overcomes the drawback of traditional type CAM providing enhance concurrent and speed data search capability.

79). Design of IP-SRAM Based Architecture for Deep Submicron on CMOS Technology

The aim of this project is to design an SRAM amalgamated with IP-SRAM architecture of 180nm technology using the VLSI platform. The advantage of this system is it minimizes the power consumed by integrated components in the circuit.

80). Design of Glitch free NAND based Digitally Controlled Delay Line for Spread Spectrum Clock Generator

Aim of this project is to overcome the drawback of NAND gate which regularly faces glitch issue during operation by using digital control delay line for spread type spectrum of clock based generator on VLSI platform.

81). Design of Performance Analysis of Different Bit Carry Look Ahead Adder using VHDL Environment

The aim of this project is to develop, test, and execute various carry look type ahead adders using the VLSI platform. In this project, the CLA used are 4-bit, 8-bit and 16-bit adders programmed in VHDL and simulated on Modelsim.

82). Design of Enhanced speed VLSI Implementation for 256-bit Parallel Prefix Type Adders

The aim of this project is to design and implement 256 bit based parallel type prefix adders using the VLSI platform. This adder is programmed in VHDL and executed on Spartan FPGA.

83). Design of Data Link Layer of OSI with Wi-Fi MAC Protocols

The aim of this project is to design a Wi-Fi device of IEEE 802.11 using VLSI technology. This device is programmed in VHDL and is employed for connecting various wireless communication devices such as laptops, computers , and mobile phones.

84). Implementation of Overlap Type Logic Cell with Power Analysis Feature

The aim of this project is to over the static power factor limitation of CMOS by employing a clock type overlap logic using the VLSI platform. This project designs both static and dynamic type edge type triggered overlap based logic flip-flip.

85). 3D Technology-Based Lifting of Discrete Wavelet Transform (DWT)

86). design of enhance speed for hardware efficient 4-bit sfq type multiplier, 87). multi-channel uart using fpga.

The aim of this project is to simplify the complexity of modern communication digital systems using VLSI technology. This project executes asynchronous type FIFO processes on FPGA. This project benefits in terms of reducing the synchronization based errors.

88). Satellite Signal Detection Design on Spartan3 FPGA Image Processing Kit

The aim of this project is to design a smart system for tracking maximum satellite signals using VLSI technology. This system aligns the satellite in the direction of obstacle fee direction and traps the maximum signal to its receiving antenna. It uses Spartan3an FPGA.

89). Design of Image Fusion System using FPGA

The aim of this project is to design a smart image fusion system for X-rays using VLSI and Matlab technology. This system considers the original image and is translates the image into pixel form using Matlab. Xilinx is used for obtaining fused type images.

90). VGA Based Ball Interface using FPGA For Image Processing

The aim of this project is to design a VGA based monitor control hardware using VLSI technology. in this system program for monitoring the bouncing ball is written in VHDL and executed on Spartan3 FPGA, once the system is activated the ball glows with specified different colors.

91). Hardware Acceleration Based Local Sensitivity Hashing for Genome Assembly

The aim of this project is to enhance the technique of easily identifying DNA in the medical industry using VLSI technology. This project considers DNA from living organisms and fragments into smaller portions and detects the DNA sequencing pattern quickly produces DNA blueprint.

92). Hardware-Based Implementation of a Video Type Processing Superblock Accelerator on FPGA

The aim of this project is to design a smart video processing system that considers data in form of raw video and processes each received unit using VLSI technology. This project uses alpha based blending technique.

93). DNA Memory Enhancement using Signal Processing

Aim of this project is to design a smart memory system that stores vast details of DNA in database using VLSI technology. This project benefits in terms of allowing the concerned research team members in reviewing the specific DNA details with one click.

94). Identifying of Hardware Trojan Horses

Trojans are Malwares that reside inside a system to corrupt system and prevent user from accessing and allow online thief to gain access to computer remotely. The aim of this project is to identify the installed Malware such as Trojans on a computer or a laptop system using VLSI technology.

95). Router Based Architecture for Junction Based Source Routing

The aim of this project is to design a smart router that bridges routing sources using the VLSI platform. Programming for the router is written in VHDL and executed on Altera based FPGA. The advantage of this project is it minimizes the delay factor and works efficiently.

Advantages of VLSI

The advantages of VLSI projects include the following.

1). Cost-effective 2). Improves circuit performance 3). Occupies less space 4). Minimizes time delay 5). Works efficiently.

Disadvantages of VLSI

The disadvantages of VLSI projects include the following.

1). Design complexity 2). Advance fabrication techniques required 3). Minimum availability of VLSI skilled engineers 4). Glitches in one component may affect other interface components.

Applications of VLSI

The application of the VLSI projects includes the following.

1). Microprocessors 2). Washing machines 3). Biometric systems 4). E-bikes 5). Mobile phones 6). Laptops, etc.

Few of the Other VLSI Project Ideas Are

1). Design of Comparator for High Speed on VLSI platform 2). VLSI based Converter design for Binary Code to Grey Code 3). Design of Digital Type Filter 4). Clock Based Gating System on VLSI 5). Design of Vedic Type Multiplier 6). CMOS Based FF Design using VLSI 7). Design of Parallel Type Processor Architecture on VLSI 8). Design of Full Adder on VLSI 9). Designing of Dynamic Type RAM using VLSI 10). Design of SRAM Based Layout on VLSI

VLSI Projects using MATLAB & Xilinx Software

The list of VLSI Projects based on MATLAB and VLSI Projects using Xilinx includes the following.

1). Designing of CDMA Based Modem & Analysis using MATLAB 2). Designing of FIR Type Filter with VHDL on MATLAB and Spartan 3 3). Designing of ModelSim & Matlab for Automotive Engineering 4). Designing Ripple Carry type Adder & Carry Skip type Adder using Xilinx 5). Designing of 32-bit Floating type Point Arithmetic Unit referring 6). Designing of Floating-Point on ALU 7). Designing of 32-bit type RISC Processor 8). Designing of Convolution Capabilities for Orthogonal Type Code 9). Design of Vending Based Machine (VM) on Xilinx and Verilog 10). Design of Parallel Prefix Adders of 256-bit using Xilinx

IEEE Projects

Following is the list of IEEE VLSI Projects.

1). VLSI Using Wireless Type Home Based Automation System via Bluetooth 2). Designing of VLSI based Architecture for Filtering of Impulse Type Noise from an Image 3). Design of Architecture for a Processor Inside A Memory Employed with Multimedia Compression Technique 4). Design Temperature Monitoring System with Cloud & IoT Platform 5). Design of OFDM Type System using IFF transform and FF Transform method 6). Design of Hamming Type Code & Implementing in Verilog 7). Design of VHDL type Finger Print Recognition aided Gabor Filter 8). Arithmetic Type Functions For Remapping with ROM Memory Based on Approximation Approaches 9). Design of FFT type Architectures using Feedforward Type Pipelined of Radix-2k 10). Design of Flip-Flops on CMOS Technology for Enhance Performance-Based VLSI Applications

Real-Time Projects

Following is the list of other real-time VLSI-based projects using VHDL code for electronics students.

1). Pragmatic Type SRAM Row Based Cache integration using Heterogeneous Based three dimensional Architecture using DRAM with TSV 2). Design of BIST for Identifying Delay and Faults in an Cluster type Field Programmable Gate Arrays 3). ASIC Design for Complex type Multiplier 4). Implementation of a Minimal Cost VLSI based filter out Impulse Noise System 5). FPGA with Space Type Vector-Based PWM Control Integrated Circuit For 3 Phase Induction type Motor Drive 6). CORDIC Algorithm and Auto Correlator implementation for OFDM type WLAN using VLSI 7). Automatic Road Based Extraction Using enhance Resolution For Satellite Quality Images 8). Design of Image-Based Segmentation Procedure with Gabor Filter for Identifying Disease in VHDL 9). Design Architecture of Minimal Complexity Turbo Based Decoder for Power-Efficient Wireless Type Sensor Networks 10). Design of enhanced Orthogonal Based Code Convolution Function on FPGA

Please refer to this link to know more about Solar Projects.

Please refer to this link to know more about CMOS and NMOS Technology .

This article covers VLSI projects list and its design, implementation, and simulation using Xilinx, VHDL, and MATLAB software and also dumped using different versions of FPGA hardware. VLSI projects always an evergreen technology that guides students and researchers to get a deep and thorough knowledge on IC technology and design more advanced equipment and more. We hope you have drawn a better brief knowledge VLSI mentioned projects list. Kindly provide your valuable suggestion by commenting in the comment box. A question for you all, “What are the different types of FPGA’s and their applications?”

  • Technologies
  • Privacy Policy

Ieee Xpert ,Ieee Xpert, ieee vlsi , ns2 , matlab , communication , java , dotnet , android , image processing projects titles 2016 2017 for mtech btech ece cse it mechanical final year students

Latest Research topics in vlsi design

Latest research topics in vlsi design.

VLSI PHD RESEARCH

If we narrow down our discussion to research in areas like electronics, electrical, computer science, artificial intelligence , wireless communication and related fields, which are the base of everything in this high-tech world. In these fields researchers have developed applications (aided with technology) for every field ranging from biomedical to aerospace and construction, which were nowhere related to electronics or even current.

As the research fields we are talking about are providing base to the developing world and providing it with reliable technologies which are being used in real time, the work of researcher becomes more wide starting with an idea to the realization of the idea in the real world in form of application or product.

To make a reliable and working model the idea of the VLSI design project ( i.e speech processing application, biomedical monitoring system etc) needs to be implemented and re-implemented, re-tested and improvised. The there are many development cycles and techniques available which eases up the implementation like:

  • Behavioral simulation
  • Software based model
  • Hardware Implementation (ASIC)
  • Programmable hardware (FPGA)
  • Co-simulation

Behavioral simulation is used at initial phase and it is not appropriate for testing the real time behavior of the system in actual environment as it is more close to systems behavior in ideal environment.

We can simulate the actual environment by using different software models (more like software models of channels used to test communication systems) but its capabilities are also limited to human capability to model the environmental conditions in mathematical equations and models.

All of us are familiar with ASIC, their high performance and hardwired implementation. These are good for final implementation but not for intermediate stages of implementation and testing. Nothing is better than ASIC for real time testing of analog  VLSI  circuits. But for digital circuits and DSP applications we have a better option of FPGA (Field Programmable Gate Array).

The hardware co-simulation is a good idea to test and monitor systems in real time. To get more details about  PhD thesis  in VLSI you can do online research or contact us.

latest Low power research topics in vlsi design

The Research Support Centre provides expert advice and support across the whole Engineering and Technical research lifecycle, from discovery through exploitation of technical and translational research. The centre has two primary functions:

  • i) to facilitate the delivery of the Engineering Sciences research strategy and to build partnerships andii) to bring together all the technical research management and support services for Students.

To achieve these goals the centre is made up of two inter-relating components. The Academic Research Support Centre consists of the Research Coordination Office, Platform Technologies team and a Translational Research Office. The Technical Research Support Centre is made up of the Joint Research Office.

The Research Support Centre encompasses a wide range of expertise and facilities. By coordinating these resources, we can provide researchers with a package of support that is integrated, high quality and streamlined – and clearly accountable.

Once a researcher has a proposal for high quality research that will benefit, they can access all the help and resources they need through one gateway. This includes support with the approval process and funding applications and help setting up technical trials.

VLSI PHD Projects

Our research interests cover low power processor architectures, low power circuit design techniques, analog and mixed signal circuit design, rapid prototyping of digital systems, reconfigurable processors, Digital arithmetic, advanced processor architectures, vlsi implementation of signal and image processing algorithms, testing verification, memory design, Embedded vlsi and asynchronous circuits.

Organization engaged with embedded commodity development and serving various business solutions such as

  • Embedded System Product Development,
  • Software services,
  • Android development,
  • Web development.

Description for “Ph.d guidance with project assitance” Ph.d/ M.Phil PROJECT ASSISTANCE We look forward to welcoming you to one of our “Research and Development Division” for all Ph.D., Research scholars. We will arrange you the following details for completing your Ph.d Degree

  • Any University Admission- We provides a step-to-step guide to completing the application form, and will help make the process as straight forward as possible.
  • Guide Arrangement
  • Survey Paper Preparation
  • Problem Identification –Problem Identification of Existing System.
  • Implementation in all domains
  • Mobile Ad hoc Networks
  • Wireless Networks
  • Image Processing
  • Grid Computing
  • Distributed Computing
  • Natural Language Processing
  • Cloud Computing
  • Soft Computing
  • Data Mining
  • Wireless Senor Networks

Delivering effective support on your Ph. D work:

Companies represents a simple and practical advice on the problems of getting started, getting organized with the working on Ph.D projects.

We make you understand the practicalities of surviving the ordeal. We just make you divide the huge task into less challenging pieces. The training includes a suggested structure and a guide to what should go in each section.

We afford complete support with real-time exposure in your Ph.D works in the field of VLSI. Our Mission drives us in the way of delivering applications as well as products with complete integrity, innovative & interesting ideas with 100% accuracy.

  • Assistance in ALL Stages of your PhD Research in VLSI from Topic Selection to Thesis Submission.
  • Creating 100% confident in submitting your thesis work.
  • Our experienced professionals support you in your research works.
  • Providing complete solutions for the Research Scholars in many advanced domains.

Technologies used in VLSI:

  • Modelsim 6.5b Simulator
  • Xilinx ISE 10.1 System generator

III. Quartus 11.1

  • Tanner v7 EDA tool

iii.        W-Edit

  • Microwind & DSCH v2

VII. P-spice

VIII. LT-spice

.        Spartan IIIe

  • Hardware Description Language

.         Verilog HDL

CORE AREA OF GUIDANCE:

  • Digital signal processing Vlsi
  • Image processing Vlsi

III.        Wireless Vlsi

  • Communication Vlsi
  • Testing Vlsi
  • Digital cmos Vlsi

VII.        low power Vlsi

VIII.        Core Vlsi

  • Memory Designs

PROJECT SUPPORT:

  • Confirmation Letter
  • Attendance Certificate

III. Completion Certificate

Preprocessing Work:

  • Paper Selection

Identifying the problem:

  • Screenshots

III.        Simulation Report

  • Synthesize Report

Report Materials:

  • Block Diagrams
  • Review Details

III.        Relevant Materials

  • Presentation
  • Supporting Documents
  • Software E-Books

VII.        Software Development Standards & Procedure – E-Book

Learning Exposure:

VIII.        Programming classes

  • Practical training
  • Project Design & Implementation

Publishing Support:

XII.        Conference Support

XIII.        Journal Support

XIV.        Guide Arrangements

Vlsi based projects like image processing projects, low power projects, matlab with vlsi projects , cryptography projects, OFDM projects, SDR projects, communication projects, zigbee projects, digital signal processing projects, and also protocol interfacing projects like uart ,i2c,spi projects.

Signal and Image processing projects can be simulated by using Modelsim 6.5b and synthesized by Xilinx 10.1 using Spartan IIIe fpga and by Quartus 11.1using altera de2 fpga. In image processing projects, the input image or video can be converted to coefficients using Matlab. Low power projects can be designed using Tanner, Microwind and spice tools.

We spotlights on imparting an overall exposure to the concept and design methodologies of all major aspects of vlsi engineering relevant to industry needs and ground-breaking thoughts with 100% pure accuracy.

latest research topics in vlsi design latest research topics in vlsi design latest research topics in vlsi design latest research topics in vlsi design latest research topics in vlsi design latest research topics in vlsi design latest research topics in vlsi design latest research topics in vlsi design latest research topics in vlsi design latest research topics in vlsi design  low power testing bist latest research topics in vlsi design latest latest research topics in vlsi design area latest research topics in vlsi design latest research topics in vlsi design latest research topics in vlsi design latest research topics in vlsi design latest research topics in vlsi design latest research topics in vlsi design

1star

IEEE Account

  • Change Username/Password
  • Update Address

Purchase Details

  • Payment Options
  • Order History
  • View Purchased Documents

Profile Information

  • Communications Preferences
  • Profession and Education
  • Technical Interests
  • US & Canada: +1 800 678 4333
  • Worldwide: +1 732 981 0060
  • Contact & Support
  • About IEEE Xplore
  • Accessibility
  • Terms of Use
  • Nondiscrimination Policy
  • Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest technical professional organization dedicated to advancing technology for the benefit of humanity. © Copyright 2024 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.

250+ Total Electronics Projects for Engineering Students

  • VLSI Projects

Very large scale integration (VLSI) technology is the enabling technology for a whole host of innovative devices and systems that have changed the way, we live. This integration allows us to build systems with many more transistors on a single IC. The EDA tools and complex hardware devices such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs) allow to develop special-purpose systems that are more efficient than general-purpose computers. In the 1960s Gordon Moore, an industry pioneer, predicted that the number of transistors that could be manufactured on a chip would grow exponentially. His prediction, now known as Moore’s Law. Moore’s ultimate prediction was that transistor count would double every 18 months. Over the past thirty years, the number of transistors per chip has doubled about once a year. The Intel microprocessors is good example in the growth in complexity of integrated circuits. The Table 1.1 shows the several generations of the microprocessors from the Intel.  

80286 2/82 134,000 1.5
80386 10/85 275,000 1.5
80486 4/89 1,200,000 1.0
Pentium™ 3/93 3,100,000 0.8
Pentium Pro™ 11/95 5,500,000 0.6

Table 1.1 Generations of Intel microprocessors

Before the invention of the VLSI technology the integrated circuits were developed using the bread board approach. In bread board approach the system is build up on the breadboard using the digital ICs available. The system is then tested for the intended results and the prototype is developed, if the system is correct, then  it was send for the silicon wafer and at this stage if error is occurred then the complete silicon wafer becomes the waste and the designer has to redesign the complete system. Thus in order to design a complete digital system on a single chip many years were required, but because of the invention of VLSI technology the time to market and the cost of design of digital ICs is reduced. This is because of the EDA tools and the programmable hardware devices available today. Table below shows the list of developed VLSI projects.

VLSI Projects List:

Sr. No. Project Title + Project details
1

In digital TV systems increased information rates requires the enhanced data capacity of the transmission stations. Therefore there is certainly definitely requirement that is strong of ways of error correction modulation and coding. The design and utilization of a modulator for transmission of digital television that is terrestrial been completed through the use of DTMB standard in this task. The VLSI that is system that is complete using VHDL coding and also the developed VHDL code is Implemented within the FPGA target device.

2 Design

In this project CAN controller is implemented utilizing FPGA. The tools which are different used whenever Actel's that is using design and the sequence of work used. This project explains the designs of multiplexer, CAN coach, an analog/digital converter and more info on the actual FPGA. The design procedure for the FPGA, preparing, coding, simulating, testing and lastly programming the FPGA is also explored. The components which are different in the FPGA are a shift -register and two state products that are connected with one another.

3

A router for junction based source routing is developed in this project. Main part of easy router includes buffering, header route and modification choice that is making. The VHDL design is of two variations of the routers for Junction Based Routing. The delay performance of routers have already been analysed through simulation. A model that is simple implemented in Altera FPGA to find the resource requirements out for the brand name brand new router designs.

4

In this project Design Space Exploration (DSE) for the Field Programmable Counter Arrays (FPCAs) and the identification of trade-offs between different parameters which describe them has been implemented. Methods for analyzing and pruning the design area are proposed to allow a exploration that is smart. The benefits and disadvantages of every solution are examined and a integration that is new based on properties of FPCAs is suggested.

5

Both digital front-end and Turbo decoder are discussed in this project. The dwelling of digital front-end for multistandard radio supporting standards that are wireless as IEEE 802.11n, WiMAX, 3GPP LTE is investigated. A design that is top-to-down. 802.11n down-converter that is digital designed from Matlab model to VHDL implementation. Both simulation and prototyping that is FPGA carried away.

6

In this project Image Processing algorithms are utilized for the reason of Object Recognition and Tracking and implement the same using an FPGA. The FPGA (Spartan 3E) contains components that are logic could be programmed to perform complex mathematical functions making them highly suitable for the implementation of matrix algorithms. The results of the FPGA execution in tracking a object that is moving found to stay positive and suitable for object tracking.

7

The design and implementation of BORPH, an operating system designed for FPGA-based reconfigurable computers has been carried out in this project. Hardware designs execute as normal UNIX processes under BORPH, accessing standard OS solutions, such as file system help. A simulink-based design flow has been used in order to develop hardware designs.

8

A hardware architecture for face detection based system on AdaBoost algorithm using Haar features has been implemented in this project. Further, the equipment design strategies image scaling that is including integral image generation, pipe lined processing as well as classifier, and parallel processing multiple classifiers to speed up the speed that is processing of face detection system has been explored.

9

This project describes an approach that is automated hardware design space research, through a collaboration between parallelizing compiler technology and high-level synthesis tools. Present results of this implementation on five multimedia kernels are shown. This technology thus considerably raises the amount of abstraction for equipment design and explores a design area much larger than is feasible for a designer that is human.

10

An FPGA-based approach to speed-up fault injection campaigns for the evaluation of the fault-tolerance of VLSI circuits has been described in this project. The proposed approach combines the efficiency of hardware-based strategies, and also the flexibility of simulation-based techniques. Further, the experimental results are supplied showing that significant speedup figures is possible with respect to state-of-the-art fault that is simulation-based techniques.

11

A 2-bit Booth encoder with Josephson Transmission Lines (JTLs) and Passive Transmission Lines (PTLs) has been implemented in this project. The circuit area for the multiplier designed with all the Booth encoder method is in comparison to that designed with the AND array technique. The proposed modified that is 4-bit encoders are created using Quartus II.

12

The cryptography circuits for smart cards have been implemented in this project. These circuits occupy little chip area, consume low power, handle a few cryptography algorithms, and offer performance that is acceptable. A hardware implementation of three standard cryptography algorithms on a universal architecture has been carried out in this project.

13

An advanced version of Spurious Power Suppression Technique (SPST) on multipliers for high speed and low power purposes has been implemented in this project. The simulation result shows that the SPST execution with AND gates owns an flexibility that is extremely high adjusting the data asserting time which not only facilitates the robustness of SPST but additionally causes a speed enhancement and energy decrease.

14

In this task three different schemes of adaptive Huffman algorithm are created called AHAT, AHFB and AHDB algorithm. Compression ratios are calculated and answers are compared with Adaptive Huffman algorithm that is implemented in C language. The performance of the proposed algorithm is improved by integrating it with the AH algorithm. The compression/decompression processors are coded Verilog that is using HDL, simulated in Xilinx ISE 9.1.

15

An efficient VLSI Architecture for Removal of Impulse Noise in Image using edge preserving filter has been implemented in this project. Further, an technology that is adaptive used to improve the results of removal of random respected impulse sound. The results shows that the proposed technique obtains better performances with regards to both evaluation that is quantitative visual quality compared to the previous lower complexity methods.

16

In this project VLSI processor architectures that support multimedia applications is implemented. The processors are classified as 1) devoted multimedia processors and 2) general-purpose processors. Dedicated multimedia processors utilize either architectures that are function-specific limited freedom but higher rate and efficiency. Advanced general-purpose processors provide the support for multimedia by integrating multimedia that are new and performing them in parallel

17

In this project architecture that is multiplier and accumulator (MAC) is proposed. Multiplication happens frequently in finite impulse response filters, fast Fourier transforms, discrete cosine transforms, convolution, and other important DSP and multimedia kernels. The objective of a good MAC is to provide a physically compact, good speed and low power chip that is consuming. The brand new SPST approach that is implementing been used. This multiplier and accumulator is made by equipping the Spurious Power Suppression Technique (SPST) on a modified Booth encoder that is controlled by a detection unit utilizing an AND gate.

18

In this project technique adiabatic utilized to reduce steadily the energy dissipation. Utilizing technique that is adiabatic in PMOS network could be minimized and some of power stored at load capacitance could be recycled instead of dissipated as temperature. However, the technique that is adiabatic extremely determined by parameter variation. MICROWIND simulations are utilized in the project.

19

The design of an Advanced Microcontroller Bus Architecture (AMBA) advanced high performance bus (AHB) protocol has been carried out in this project. Operations like easy write that is read burst read write and out of purchase read write have actually been talked about. The look of the Protocol is simulated Modelsim that is using which the fundamental blocks such as Master and Slave. The coding language used is VHDL.

20

The verification and design for the concentrator of a Knockout Asynchronous Transfer Mode (ATM) switch fabric has been carried out by utilizing the VIS device in this project. The RTL design that is structural well as a higher-level model that is behavioral of Knockout switch concentrator in Verilog HDL has been developed.

21

This project presents a way of behavioral synthesis of asynchronous circuits which builds on top of syntax directed translation, and which allows the designer to perform design that is automatic research led by area or rate constraints. Further, an asynchronous implementation template consisting of a data-path and a control unit and its particular execution utilizing the hardware description language that is asynchronous

22

The method how to build an Advanced microcontroller Bus Architecture (AMBA) compliant microcontroller as an Advanced High performance Bus (AHB) slave is presented in this project. The microcontroller is made for system memory control with the memory that is main of SRAM and ROM.

23

In this project Xilinx ISE tool is used for simulation, logical verification, and further synthesizing the binary adder which may be the critical element in many electronic circuit designs including digital signal processors (DSP) and microprocessor datapath units. This project investigates three types of carry tree adders.

24

A 32 bit floating point arithmetic unit with IEEE 754 Standard has been designed using VHDL code and all operations of addition, subtraction, multiplication and division are tested on Xilinx in this project. Thereafter, Simulink model in MATlab has been designed for verification of VHDL rule of that Floating Point Arithmetic Unit in Modelsim.

25

The cyclic redundancy check (CRC) architecture has been designed to be field reprogrammable so that it is fully flexible in terms of the polynomial deployed and the input port width in this project. The circuit includes an embedded setup controller that has a configuration that is low and hardware cost. The circuit is synthesised and mapped to 130 nm UMC cell that is standard technology.

26

This project presents the silicon proven design of a novel network that is on-chip support guaranteed traffic permutation in multiprocessor system-on-chip applications. On-chip interconnection networks or Network-on- Chips (NoCs) are becoming the scaling that is de-facto strategies in Multi-Processor System-on-Chip (MPSoC) or Chip Multiprocessor (CMP) environment.

27

This project concentrated on developing model that is hardware systolic multiplier using Very High Speed Integrated Circuits Hardware Description Language (VHDL) as a platform. The design is simulated modelsim that is using and synthesized on Spartan 3 FPGA board.

28

In this project VHDL environment is used for floating point arithmetic and logic unit design pipelining. The novelty in the ALU design may be the Pipelining which provides a performance that is high. Each module is split into sub-modules. Two selection bits are combined to choose a in the ALU design are recognized VHDL that is using functionalities are validated through VHDL simulation. Simulation and synthesis result find out in the Xilinx12.1i platform.

29

The principle and commands of Double Data Rate Synchronously Dynamic RAM (DDR SDRAM) controller design are explained in this project. The operations of DDR SDRAM controller are realized through Verilog HDL. The proposed architecture design of DDR SDRAM controller is utilized as IP core into any FPGA based embedded system requirement that is having of rate operation.

30

A novel simple address mapping scheme and the modified radix 4 FFT is proposed in this project. FPGA was majorly utilized to build up the ASIC IC's to that was implemented. The design is simulated and

synthesized the 256 point FFT with radix 4 VHDL that is using coding 64 point FFT Hardware mplementation

31

The objective that is main of project is to create and implement of 32 bit Reduced Instruction Set Computer (RISC) processor using XILINX VIRTEX4 Tool for embedded and portable applications. This processor range from the Arithmetic Logic Unit, Shifter, Rotator and Control unit. The module functionality and performance issues like area, power dissipation and propagation wait are analyzed Virtex4 XC4VLX15 XILINX that is using tool.

32

In this project VHDL model of smart sensor is proposed to get solution to your challenge of designers. The signal is first sensed using signal sensing process then it is conditioned and processed using VHDL to achieve good result. The program that is VHDL as the smart sensor as above mentioned step. The VHDL allows the simulation that is complete of system.

33

This project presents the designing of Proportional-Integral-Derivative (PID) controller according to Fuzzy algorithm using VHDL to utilize in transportation system that is cruising. The system that is cruising Fuzzy concept has developed to prevent the collisions between vehicles on the road. The contrast of simulation results between Matlab and VHDL are presented for designing the PID-type hardware execution. The synthesis device from Quartus-II environment is chosen to synthesize the created VHDL codes for obtaining the Register Transfer Level (RTL)

34

In this project cordless stepper motor controller designed using VHDL and is implemented on SPARATAN Field Programmable Gate Array (FPGA). The proposed motor controller is controlled through the use of Pulse Width Modulation (PWM) Technique therefore providing the really precision that is high. In this system GUI is designed using LABVIEW to give the control parameter to your wireless stepper motor that is connected.

35 C Bus Controller

This project is concerned with all the design of I2C bus controller and the interface involving the devices that are microcontroller (AT89C51) and EEPROM (AT24C16). The microcontroller and EEPROM are interfaced through I2C bus. Data send, read and write particularly these operations are executed and the behavior of I2C protocol is analyzed. In later section the master that is i2C is designed in verilog HDL. By describing the look in HDL, practical verification of the design can be achieved early within the design cycle.

36

An attempt is made to implement the solar power saver system for street lights and automatic traffic control unit in this project. The proposed system is implemented with MAX3032 Altera CPLD with 32 cells that are macro. An sensor that is infrared is set up in the streets to understand the presence of traffic. Proposed cost system that is effective just saves the power instead it reduces the use of conventional power. The proposed system logic is implemented using VHDL.

37

In this project model for an autonomous robot that is mobile (MRC) hardware with navigation concept utilizing Fuzzy Logic Algorithm (FLA) has been designed. The designed hardware architecture of autonomous mobile robot can be easily utilized in unstructured environments appropriately to avoid collision with obstacles by turning to your angle that is proper. The model of MRC algorithm is first developed in MATLAB. The developed model of MRC has translated into VHDL model for hardware implementation, followed by the synthesis tool, Quartus II from Altera to get synthesized logic gate levels after getting the confidence on MATLAB results. The codes that are synthesized downloaded into Field Programmable Gate Array (FPGA) board to verify the correctness of the MRC algorithm in behavioral level for VLSI implementation.

38

The design and implementation of a real-time traffic light control system based on Field programmable Gate Array (FPGA) technology is reported in this project. The traffic light control system is made with VHDL language. Its function ended up being verified with simulation. From then on, the VHDL design downloaded to FPGA board hardware to confirm its function in test.

39

This project targets the look of a power that is low high performance FPGA based Digital Space Vector Pulse Width Modulation (DSVPWM) controller for three stage voltage supply inverter. The proposed DSVPWM method algorithm ended up being synthesized and implemented Quartus II and Cyclone II FPGA, to focus on device.

40

In this project VHDL implementation of complex quantity multiplier using ancient mathematics that are vedic conventional modified Booth algorithm is presented and compared. The idea for designing the unit that is multiplier adopted from ancient Indian mathematics “Vedas”. The UrdhvaTiryakbhyam sutra was selected for implementation since it’s applicable to all full instances of multiplication.

41

An approach is presented by this project towards VLSI implementation of the Discrete Wavelet Transform (DWT) for image compression. The look follows the JPEG2000 standard and will be used for both lossy and compression that is lossless. In order to reduce complexities for the design, linear algebra view of DWT and IDWT has been utilized.

42

The Simulation of Gabor filter for fingerprint recognition has been carried out using Verilog HDL in this project. The applying of Gabor Filter technique to enhance the fingerprint image and it’s utilized to define the ridges and valley parts of fingerprints is by convoluting the image pixel with Gabor filter coefficient. The result that is experimental the sign convoluted with the Gabor coefficient.

43

A single precision floating point fused add-subtract unit and fused dot -product unit is presented that performs simultaneous floating point add and multiplication operations in this project. It takes to perform a significant element of single addition, subtraction and dot product using implementation that is parallel. This unit uses the IEEE 754 precision that is single and supports all rounding modes.

44

In this project, FPGA implementation of orthogonal code convolution is presented by using Xilinx and Modelsim softwares. Orthogonal Code is certainly one of the codes that can identify errors and correct data that are corrupted. The technique was implemented using FPGA.

45

This project enumerates power that is low high speed design of SET, DET, TSPC and C2CMOS Flip-Flop. As these flip-flop have actually small area and low power usage, they may be used in various applications like digital VLSI clocking system, buffers, registers, microprocessors etc. The Flip -Flops are analysed at 90nm technologies. The above mentioned designed Flip-Flops and Latches are compared in regards to its area, transistor count, energy dissipation and propagation wait DSCH that is using and tools.

46

This project presents a method to reduce the computation and memory access for variable block size motion estimation (ME) pixel truncation that is using. Previous work has focused on implementing pixel truncation utilizing a set block size (16×16 pixels) Further, the effect of truncating pixels for smaller block partitions and proposed a method has been analysed.

47

In this project power gating implementations that mitigate power supply noise has been investigated. To figure out the implementation that is best, a test chip in 65nm process. Experimental results with dimension and simulation reveal that the power-gated circuit with body-tied structure in triple-well is the implementation that is best through the after three points; energy supply sound due to rush current, the share of decoupling capacitance throughout the rest mode and the leakage reduction many thanks to energy gating.

48

In this project universal receiver that is asynchronous (UART) is a protocol utilized in serial communication specifically for short distance information exchange. The design can detect errors that are various as framework error, over run error, parity error and break mistake. The whole design of universal receiver that is asynchronous is functionally verified using ModelSim.

49

In this project High performance, energy logic that is efficient VLSI circuits are implemented. Further, the design of the Wallace tree multiplier, Baugh wooley and Array multiplier using fixed logic design, dynamic logic style and compound constant logic style that is delay. The performance of power delay product of Wallace tree multiplier, array multiplier and Baugh wooley multiplier utilizing compound constant delay logic style is reduced considerably while compared to fixed and logic style that is dynamic

50

In this project 4 bit Flash Analog to Digital converter is implemented. The proposed ADC consist of the comparators and the MUX based decoder. Proposed Comparator eliminate the use of resistor ladder in the circuit. All of the input of comparators are linked to the input that is common. Based upon the voltage that is internal of and the input voltage production may be "0" or "1".

51

A new leading-zero anticipatory (LZA) logic for high-speed floating-point addition and subtraction is proposed in this project. The pre-decoding for normalization concurrently with addition for the significant is completed in this logic. The usage of simple algebra that is Boolean the proposed logic to be constructed from a simple CMOS circuit.

52

The FPGA implementation of a Linear feedback shift resister (LFSR) based pseudo random pattern generator in this project. This LFSR has the characteristics of high speed, low power usage plus it is especially matched in processing environment where consistent distribution random numbers are needed. A application that is typical of pattern generator considered in this work is the screening of micro-electro-mechanical-system (MEMS).

53

This project presents a novel low-transition Linear Feedback Shift Register (LFSR) that is based on some brand new observations about the production series of a LFSR that is conventional. The proposed design, called LFSR that is bit-swapping, consists of an LFSR and a 2 × 1 multiplexer. Experimental results on ISCAS'89 benchmark circuits show up reductions in average and peak power.

54

An efficient algorithm for implementation of vending machine on FPGA board is proposed in this project. The proposed algorithm is implemented in Verilog HDL and simulated Xilinx ISE simulator that is using tool. The design is implemented on Xilinx Spartan-3A FPGA development board.

55

A study is undertaken for determining the number of pipeline stages required for the DWT computation so as to synchronize their operations and utilize their hardware resources efficiently are implemented in this project in order to enhance the inter-stage parallelism.

56

The efficient cache controller suitable for use in FPGA-based processors is implemented using VHDL in this project. With reference to set cache that is associative cache controller is made. Spatial locality of reference can be used for tracking cache miss induced in cache memory.

57

In this project efforts are being designed to automate the billing systems. Despite the fact that more accurate and faster meter readings have seen the light of day, bill payment continues to be according to a procedure that is old. This task implements the electricity bill meter that is prepaid.

58

The behavior of the SRL16 CAM design methodology is described using VHDL and implemented using FPGA technique in this project. Then, the performance of the method ended up being in comparison to other CAM that is traditional techniques. The proposed RCAM is configured and used as the main element of different network products and also the successful implementations of this RCAM prove its Suitability to be utilized in various performance that is high devices.

59

This project concentrates on the implementation and simulation of 4-bit, 8-bit and carry that is 16-bit -ahead adder using VHDL and compared for their performance. The simulation is done using ModelSim SE 6.3f and the performance improvements in propagating the carry and generating the sum in comparison with the standard carry look ahead adder designed in the technology that is same.

60

A new approach to redesign the basic operators used in parallel prefix architectures is implemented in this project. The number of multiplexers contained in each Slice of an FPGA is considered right here for the redesign of the operators that are basic in parallel prefix tree. This design that is new implemented with 128-bit width operands of numerous parallel prefix adders on Xilinx Spartan FPGA. The experimental results suggest that the brand new approach of fundamental operators make a few of the prefix that is parallel architectures faster and area efficient

61

The radio frequency identification (RFID) tag–reader mutual authentication (TRMA) scheme has been implemented in this project. Two enhanced verification protocols for generating the Pad Gen function are described. Further, a protocol for RFID label –reader mutual authentication scheme is proposed which is efficient that is hardware. The proposed protocol is described in Verilog HDL and simulated Xilinx ISE design suite.

62

In this project architecture that is power-efficient of side triggered flip flops with clock Overlap based logic has been implemented. The consequence of this logic is that power that is static gets enhanced in CMOS technology. Further, the energy contrast is done between the logic that is overlap conventional dynamic C2MOS logic making use of Cadence tool and 180nm GPDK technology.

63

In this task two adder compressors architectures addressing high-speed and power that is low been implemented. Adder compressors are utilized to implement arithmetic circuits such as for instance multipliers and signal that is digital units like the Fast Fourier Transform (FTT). Further, this work presents an architecture that create the XOR and XNOR signals simultaneously, this reduce internal glitches power that is hence dynamic well.

64

This project handles utilization of a USB Core specifically UTMI and protocol layer module on FPGA. The design is carried out by writing rule in verilog HDL which is then confirmed and synthesized Xilinx that is using XST. The end result is verified using testbench waveform.

65

In this project unpipelined architecture of a 8 bit Pico Processor (pP) and how its overall through put can be increased by implementing pipelining has been analyzed. Pico processor is an 8 bit processor which is comparable to 8 bit microprocessors for small applications that are embedded it’s meant for educational purpose

66

The design and hardware implementation of the main controller for a remote sensing system that can be communicated through the Global System for Mobile (GSM) Network has been implemented in this project. This system provides a complete, low cost, effective and easy to use means of 24 hours real time monitoring and sensing system that is remote. The design has been described VHDL that is using and in hardware using Field Programmable Gate Array (FPGA).

67

This project generates Multiple Single Input Change (MSIC) vectors in a pattern, is applicable each vector to a scan chain is an SIC vector. A MSIC-TPG and Accumulator based TPG are created and developed a Johnson that is reconfigurable counter a scalable SIC counter to generate a class of minimum transition sequences. The proposed accumulator based TPG achieves reduced area and power that is average during scan-based tests and also the top power in the circuit under test. The test patterns are simulated using MODELSIM and the results are validated by writing VHDL coding.

68

In this project faster column compression multiplication has been attained by utilizing a combination of two design techniques: partition for the partial items into two parts for independent parallel column compression and acceleration for the final addition utilizing a adder that is hybrid. Based on the proposed strategies 8, 16, 32 and 64-bit Dadda multipliers are developed and compared with the Dadda that is regular multiplier. The performance of the proposed multiplier is analyzed by evaluating the wait, area and power, with 180 process that is nm.

69

In this project cycle that is single test structure for logic test eliminates the power consumption problem of conventional shift based scan chains and reduces the activity during shift and capture cycles. Further, a new cycle that is single test structure for logic test is implemented. This leads to more circuit that is realistic during stuck -at and at-speed tests. The work is carried out using language simulated modelsim6.4b And Xilinx that is synthesized ISE10.1

70

In this project a Low – Voltage Low-Dropout(LDO) Voltage Regulator that can operate with a very small Input–Output Differential Voltage with nm CMOS technology in turn increasing the Packing Density, provides for the new approaches  towards power management is proposed. The compact area of the proposed LDO regulator leads to a chip area efficient low drop-out Voltage Regulator which finds its applications for portable electronics.

Useful Resources

  • Mini Projects
  • MATLAB Projectss
  • Arduino Projects

We're a diverse group of EE students, working on digital and analog circuit design, microfluidics, medical imaging, and more. Take a look at the projects page to see some of the things we're working on.

New Website:         https://vlsi.stanford.edu

ElProCus – Electronic Projects for Engineering Students

Latest List of VLSI Projects for Electronics Engineering Students

The term VLSI stands for “Very Large Scale Integration Technology” which involves designing integrated circuits (ICs) by combining thousands of transistors logically into a single chip by different logic circuits . These ICs eventually reduce the occupied circuit space when compared to the circuits with conventional ICs. Computational power and space utilization are the main challenges of the VLSI design. Implementing VLSI projects opens up a challenging and bright career for students as well as researchers. Some of the new trending areas of VLSI are Field Programmable Gate Array applications (FPGA), ASIC designs, and SOCs. A list of some of the VLSI projects is given below for those students who are earnestly seeking projects in this field. This article discusses an overview of VLSI projects based on FPGA, Xilinx, IEEE, Mini, Matlab, etc are listed below. These projects are very helpful for engineering students, M.tech students.

VLSI Projects for Engineering Students

VLSI Projects with abstracts for electronics engineering students are discussed below.

VLSI projects

1). Transform of Discrete Wavelet-based on 3D Lifting

This project helps in providing highly precise images by using the coding of an image without losing its data. To attain this, this process implements a lifting filter depending on the transform of 3D discrete wavelet VLSI architecture.

2). Designing of SFQ Multiplier with 4-bit with Efficiently through High-Speed Hardware

This project is mainly used for implementing a modified booth encoder (MBE) with 4-bit SFQ based multiplier . This multiplier provides good performance when compared with the conventional booth encoder. This project is mainly used in the applications of critical delay.

3). Cryptography Processor used in Smart Cards with an Efficient Area

This project is used to implement three cryptography algorithms supported by both private & public keys used in smart card applications for providing extremely secured user verification & data communication .

4). A High-Speed or Low-Power Multiplier with Spurious Power Suppression Method

This proposed system filters outs the useless false signals of arithmetic units for avoiding unnecessary data transmission which does not influence the last computing results. This system uses an SPST method for multipliers to achieve low power and high-speed data transmission.

5). Compression & Decompression of a Lossless Data Algorithm

This project is mainly implemented for 2-stage hardware architecture depending on the PDLZW (Parallel Dictionary LZW) algorithm feature as well as the Adaptive Huffman type algorithm which is used for both the applications of lossless data compression & lossless decompression.

6). The Architecture of Turbo Decoder with Low-Complexity for Energy-Efficient WSNs

The proposed system is used to reduce the total energy consumption throughout data transmission of WSNs through the decomposing algorithm of LUT-Log-BCJR to basic ACS (Add Compare Select) operations.

7). VLSI Architecture for Removing Impulse Noise of an Image with Efficiently

This proposed system mainly used to enhance the image quality visually for avoiding the chances of being corrupted with impulse noise to implement an efficient VLSI architecture with the help of an edge-preserving filter.

8). The Architecture of an In-Memory-Processor used for Compression of Multimedia

This proposed system provides a low complexity architecture for a processor in memory to support multimedia applications namely image compression, video through applying enormous single-instruction, multiple data concepts & instruction word.

9). Timing Synchronization Technique with a Symbol Rate for Wireless OFDM Systems with Low Power

This proposed system mainly used to improve the act of wireless OFDM (Orthogonal Frequency Division Multiplexing ) system through decreasing the power of the entire baseband with the help of a clock generator with phase tunable & dynamic sample-timing controller.

10). Accumulator based Low Power & High-Speed Multiplier Implementation with SPST Adder & Verilog

This project is used to design a low power & high-speed MAC (multiplier and accumulator) through accepting the false suppression method of power on an MBE (modified booth encoder). By using this design, the power dissipation of entire switching can be avoided.

11). Robot Processor Design & Implementation by Enabling Anti-collision with RFID Technology

The proposed system is mainly used to implement a robot processor with anti-collision to avoid the physical collision of robots in the environment of multi-robot. This algorithm is mainly implemented using VHDL & RFID technology.

12). Designing of Logic Circuit with Power Efficient using Adiabatic Method

This system demonstrates the logic circuit design by efficiently with adiabatic method when compared through conventional CMOS design with the help of circuits using NAND & NOR gates . By using the adiabatic method, the dissipation of power within the network can be reduced as well as recycles the stored energy within the load capacitor.

3). Encryption System for Enhancing the Computing Speed of the System

The main intension of this project is to enhance data transmission security to improve the speed of computing by implementing the algorithm of AES using FPGA. So, this simulation, as well as mathematical design, can be carried out with the help of the VHDL code.

14). IP Block of AHM or Advanced High-Performance Bus

This project is mainly used to design an architecture of the Advanced Microcontroller Bus (AMB) by using AHBN (Advanced High-Performance Bus). This project can be designed with VHDL code by implementing the blocks like master & save.

15). DSM based Multimode RF Transceiver with a Multichannel

This system mainly used to design a multimode transmitter & receiver architecture and RF multichannel with Delta-Sigma modulator. This proposed system uses a VHDL language to implement two architectures.

16). The Concentrator of Knockout Switch using an Asynchronous Transfer Mode

By using this project, a knockout switch based on asynchronous transfer can be designed with the help of tools like VHS & VHDL. This knock out switch can be used in the networks of virtual circuit packet as well as applications of the datagram.

17). Asynchronous Circuits Behavioral Synthesis

This project is mainly used to provide the behavioral synthesis technique used for asynchronous circuits. Both the templates like the balsa & asynchronous implementations are the main elements within the design.

18). AMBA Design using Compliant Memory Controller of AHB

This project is used to design an MC (memory controller) depending on AMBA (Advanced Microcontroller Bus Architecture) for system memory controlling using main memory like SRAM & ROM.

19). Carry Tree Adder Implementation

Carry tree adder based on VLSI design are called as the best performance adders as contrasted through usual binary adders. The adders which are implemented by this project are spanning tree, kogge-stone, and sparse kogge-stone.

20). CORDIC Design based Rotation of Fixed Angle

The main concept of this proposed system is to turn vectors using fixed angles. These angles are necessary for games, robotics, image processing , etc. By using this project, vector rotation can be achieved by using specific angles by the design of CORDIC (coordinate rotation digital computer).

21). FIR Filter Design with Distributed Arithmetic of Lookup Table

This proposed system mainly enhances FIR filter performance by designing it using distributed arithmetic of a 3-dimensional lookup table in place of the multiplier. So this design can be implemented using softwares like FPGA & Xilinx.

22). Push-Pull Pulsed Latches with High Speed & Low Power Conditional

This project is used to execute energy-efficient & high-performance pulsed latches mainly used for VLSI systems by using new topology. Because this topology mainly depends on a final stage push-pull driven using two divide lanes through a conditional pulse generator.

23). Arithmetic Coder VLSI Architecture in SPIHT

This proposed system enhances the throughput of the method of arithmetic coding in set partitioning in hierarchical trees (SPIHT) image compression with the high-speed architecture depending on FPGA.

24). Noise Suppression of ECG Signal based on FPGA

This project is used to contain the noise within ECG signals through two median filters with 91 & 7 sample point sizes respectively. So this process can be attained through implementing the FPGA design based on VHDL code.

25). VLSI based High-Performance Image Scaling Processor with Low Cost

This project is used to implement an algorithm for image scaling processor based on VLSI with less memory and high performance. The proposed system design mainly contains combining of filter, reconfigurable dynamic methods & hardware sharing to decrease the cost.

26). Systolic Array Architecture Design & Implementation Efficiently

The main concept of this project is to design a hardware model used for the systolic array multiplier. This array can be mainly used to execute binary multiplication with the help of the VHDL platform. The proposed system design can be implemented using FPGA & Isim software.

27). QPSK Design & Synthesis using VHDL Code

QPSK is one of the main modulation methods. This method is used in the applications of satellite radio. This modulation technique can be implemented through reversible logic gates. The designing of the QPSK technique can be done with the help of the VHDL code.

28). DDR SDRAM Controller Design & Implementation with High Speed

The proposed system is used to design a DDR SDRAM controller for transferring the burst data depending on high speed to synchronize this data in between the circuitry of embedded system & DDR SDRAM. By using the VHDL language, the code can be developed.

29). 32 Â-bit RISC Processor Design & Implementation

The main concept of this project is to implement a 32 bit RISC (Reduced Instruction Set Computer) with the help of a tool like XILINK VIRTEX4. In this project, 16 instruction sets are designed wherever every instruction can be executed in a single CLK cycle using the five-phase pipelining method.

30). Bus Bridge Implementation between AHB & OCP

The proposed system is used to design a bus bridge between two protocols namely common & standard. The communication protocols like AHB (Advanced High-performance Bus) & OCP (Open Core Protocol) are very popular which are used in the applications of SoC (System On-chip) .

VLSI Projects Ideas for Engineering Students

The list of VLSI projects based on FPGA, MatLab, IEEE, and Mini Projects for engineering students is listed below.

VLSI Projects for M. Tech Students

The list of VLSI projects based on M. Tech Students includes the following.

  • Area-Efficient & Highly Reliable RHBD based I0T Memory Cell Design used in Aerospace Applications
  • Phase Detector with Multilevel Half-Rate used for CLK & Data Recovery Circuits
  • Comparator with a Low Power & High Speed used for Precise Applications
  • Gated Voltage Level Translator with a High-Performance & Integrated Multiplexer
  • CNTFET based Ternary Adder with High-Performance
  • Magnitude Comparator Design with Low Power
  • Design of Threshold Logic Gate with Current-Mode for Delay Analysis
  • Mixed-Logic Line Decoders Design with Low-Power & High-Performance
  • Sleep Convention Logic Testability Design
  • Voltage Level Shifter for Dual-Supply Applications with a High-Speed & Power-Efficient
  • Low Power & Low Voltage Double-Tail Comparator Design & Analysis
  • Flip-Flop Design based on Pulse-Triggered with Low-Power using a Signal Feed-Through Method
  • Efficient Circuits Design based on Runtime Reconfigurable FETs
  • Delay Analysis of Logic Gate Designs with Current-Mode Threshold

The FPGA based VLSI projects for engineering students and CMOS VLSI design mini-projects are listed below.

  • SEU Hardened Circuits Design & Characterization for FPGA based on SRAM
  • A Compact Memristor based CMOS hybrid LUT Design & Potential Application used in FPGA
  • Ultrasonic Sensor based Implementation of FPGA for Distance Measurement
  • Implementation of FPGA for Booth Multiplier with Spartan6 FPGA
  • Discrete Wavelet Transform based on Lifting with Spartan3 FPGA
  • ARM Controller in Robotics using FPGA
  • FPGA based UART with Multichannel
  • Suppression of ECG Signal Noise using FPGA
  • UTMI based FPGA Implementation & USB 2.0 Protocol Layer
  • Implementation of Median Filter with Spartan3 FPGA
  • AES Algorithm based Implementation of FPGA
  • Security Alert System based on PIC for Implementation of FPGA with Spartan 3an
  • FPGA Implementation to Design the Controller for Remote Sensing Systems
  • Image Processing Kit of FPGA using Image Filtering of Linear & Morphological
  • Spartan3 FPGA based Medical Fusion Image Implementation

The list of VLSI mini projects using VHDL code includes the following.

  • Comparator with High Speed using VLSI
  • A multiplier of Floating-Point using VLSI
  • VLSI based Conversion of Binary to Grey
  • Digital Filter
  • CLK Gating based on VLSI
  • Vedic Multiplier
  • CMOS FF using VLSI
  • The architecture of Parallel Processor using VLSI
  • VLSI based Full Adder
  • Design of DRAM/Dynamic Random Access Memory based on VLSI
  • SRAM Layout based on VLSI
  • VLSI based Digital Signal Processor
  • VLSI based Multiplexer
  • Designing of MAC Unit based on VLSI
  • VLSI based Differentiator
  • VLSI based FFT or Fast Fourier Transform
  • The architecture of Discrete Cosine Transform based on VLSI
  • 16-bit Multiplier Design using VLSI19
  • VLSI based Designing of FIFO Buffer
  • High-Speed Accelerator based on VLSI

VLSI Projects using MATLAB & Xilinx

The list of VLSI projects based on MATLAB and VLSI Projects using Xilinx includes the following.

  • CDMA Modem Design & Analysis with MATLAB
  • FIR Filter Design using VHDL on FPGA & MATLAB based Analysis
  • ModelSim & Matlab or Simulink based Simulation of System for Automotive Engineering
  • Xilinx based Adders like Ripple Carry & Carry Skip
  • Arithmetic Unit based on 32-bit Floating Point
  • Floating Point-based ALU
  • RISC Processor based on 32-bit
  • Convolution Capabilities of Orthogonal Code
  • Xilinx and Verilog based Vending Machine
  • Xilinx based Parallel Prefix Adders with 256-bit
  • Protocol for Mutual Authentication using Xilinx
  • Access Structure with Single-Cycle for Logic Test using Xilinx
  • UTMI & Protocol Layer based USB2.0 using Xilinx
  • Configuration of Data Compression And Decompression using Xilinx FPGA
  • Xilinx 4000 based BIST & Spartan Series based FPGAs
  • IIR Filter based on MATLAB & VLSI
  • FIR Filter using MATLAB

IEEE Projects

The list of IEEE VLSI Projects is listed below.

  • VLSI based Wireless Home Automation System using Bluetooth
  • Removing of Impulse Noise within Image by using an Efficient Architecture of VLSI
  • The Architecture of a Processor-In-Memory for Multimedia Compression
  • Monitoring of Temperature System using Cloud & IoT
  • OFDM System Implementation with IFFT & FFT
  • Hamming Code Design & Implementation with Verilog
  • VHDL based Finger Print Recognition using Gabor Filter
  • Arithmetic Functions Remapping with ROM Depending on Approximation Approaches
  • Analysis of High Efficiency & Low-Density Performance of Parity-Check Code Decoder in Low-power Applications
  • FFT Architectures with Feedforward of Pipelined Radix-2k
  • Flip-Flops Design for VLSI Applications using CMOS Technology with High Performance
  • FIR Filter Design with Lookup Table by Distributed Arithmetic
  • VLSI based Low Cost & Enhanced Image Scaling Processor
  • ASIC Implementation & Design of an Advance Turbo Encoder & Decoder with 3GPP LTE
  • Push-Pull Pulsed Latches with Low Power & High-Speed Conditional
  • Enhanced Scan in Low Power Scan Testing
  • Arithmetic Coder VLSI Architecture for SPIHT
  • Implementation of VHDL for UART
  • VLSI based Voltage Regulator with Low Drop Out
  • Flash ADC Design with Enhanced Comparator Scheme
  • Low Power Multiplier Design with Compound Constant Delay Logic Style
  • Double Tail Comparator with High Performance & Low Power
  • Flash Storage System with High Performance depending on Write Buffer & Virtual Memory
  • Low Power FF based on Sleepy Stack Approach
  • LFSR Power Optimization for Low-power BIST Implemented in HDL
  • Vending Machine Design & Implementation with Verilog HDL
  • Accumulator Design based on the Generation of 3-Weight Pattern with LP-LSFR
  • Reed-Solomon Decoder with High-Speed & Low-Complexity
  • Faster Dadda Multiplier Design Technique
  • Digital Demodulation based Receiver of FM Radio
  • Generation of Test Pattern with BIST Schemes
  • Implementation of VLSI Architecture with High-Speed Pipeline
  • On-Chip Bus OCP Protocol Design using Bus Functionalities
  • Phase Frequency Detector & Charge Pump Design used for High-Frequency Phase-Locked Loop
  • Cache Memory & Cache Controller Design with VHDL
  • ASTRAN based Implementation of Low Power 3-2 & 4-2 Adder Compressors
  • Prepaid Electricity Billing System using an On-Chip Design
  • Overlap Implementation using Logic cell & Its Power Analysis
  • Carry Look Ahead Adder with Different Bit Performance Analysis using VHDL
  • Data Link Layer Design with Wi-Fi MAC Protocols
  • Implementation of FPGA for Mutual Authentication Protocol with Modular Arithmetic
  • PWM Signal Generation using FPGA & Variable Duty Cycle

Real-Time Projects

The list of VLSI real-time projects mainly include VLSI mini projects using VHDL code and VLSI software projects for ECE engineering students.

  • Pragmatic Integration of SRAM Row Cache in Heterogeneous 3-D DRAM Architecture Using TSV
  • Built-in Self-Test Technique for Diagnosis of Delay Faults in Cluster-Based Field Programmable Gate Arrays
  • ASIC Design of Complex Multiplier
  • A Low-Cost VLSI Implementation for Efficient Removal of Impulse Noise
  • FPGA Based Space Vector PWM Control IC For Three Phase Induction Motor Drive
  • VLSI Implementation of Auto Correlator and CORDIC Algorithm for OFDM Based WLAN
  • Automatic Road Extraction Using High-Resolution Satellite Images
  • VHDL Design for Image Segmentation Using Gabor Filter for Disease Detection
  • A Low Complexity Turbo Decoder Architecture for Energy Efficient Wireless Sensor Networks
  • Improvement of The Orthogonal Code Convolution Capabilities Using FPGA Implementation
  • Design and Implementation of Floating Point ALU
  • CORDIC Design for Fixed Angle of Rotation
  • Product Reed-Solomon Codes for Implementing NAND Flash Controller on FPGA Chip
  • Statistical SRAM Read Access Yield Improvement Using Negative Capacitance Circuits
  • Power Management of MIMO Network Interfaces on Mobile Systems
  • Design of Data Encryption Standard for Data Encryption
  • Low Power and Area Efficient Carry Select Adder
  • Synthesis and Implementation of UART Using VHDL Codes
  • Improved Architectures for a Fused Floating-Point Add-Subtract Unit
  • An FPGA Based 1-Bit All-Digital Transmitter Employing Delta-Sigma Modulation with RF Output for SDR
  • Optimizing Chain Search Usage in The BCH Decoder for High Error Rate Transmission
  • Digital Design of DS-CDMA Transmitter Using Verilog HDL and FPGA
  • Design and Implementation of Efficient Systolic Array Architecture
  • A VLSI-Based Robot Dynamics Learning Algorithm
  • A Versatile Multimedia Functional Unit Design Using the Spurious Power Suppression Technique
  • Design of Bus Bridge between AHB and OCP
  • Behavioral Synthesis of Asynchronous Circuits
  • Speed Optimization of an FPGA Based Modified Viterbi Decoder
  • Implementation of I2C Interface
  • A High-Speed/Low-Power Multiplier Using an Advanced Spurious Power Suppression Technique
  • Clamping Virtual Supply Voltage of Power Gated Circuits for Active Leakage Reduction and Gate Oxide Reliability
  • FPGA Based Power Efficient Channelizer for Software Defined Radio
  • VLSI Architecture and FPGA Prototyping of a Digital Camera for Image Security and Authentication
  • Operation Improvement of Indoor Robot
  • Design and Implementation of an ON-Chip Permutation Network for Multiprocessor System-On-Chip
  • A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems
  • DMA Controller (Direct Memory Access ) Using VHDL/VLSI
  • Reconfigurable FFT Using CORDIC Based Architecture for MIMI-OFDM Receivers
  • Spurious Power Suppression Technique for Multimedia/DSP Applications
  • The efficiency of BCH Codes in Digital Image Watermarking
  • Dual Data Rate SD-RAM Controller
  • Implementing Gabor Filter for Fingerprint Recognition Using Verilog HDL
  • Design of a Practical Nanometer Scale Redundant via Aware Standard Cell Library for Improved Redundant via 1 Insertion Rate
  • A Lossless Data Compression and Decompression Algorithm and Its Hardware Architecture
  • A Framework for Correction of Multi-Bit Soft Errors
  • Viterbi-Based Efficient Test Data Compression
  • Implementation of FFT/IFFT Blocks for OFDM
  • Wavelet-Based Image Compression by VLSI Progressive Coding
  • VLSI Implementation of Fully Pipelined Multiplier Less 2d DCT/IDCT Architecture for Jpeg
  • FPGA-Based Fault Emulation of Synchronous Sequential Circuits

Thus, this is all about the list of VLSI projects for engineering, M.Tech students which are helpful in selecting their final year project topic. After spending your valuable time while going through this list, we believe that you have got a fairly good idea of selecting the project topic of your choice from the VLSI projects’ list, and hope that you have enough confidence to take up any topic from the list. For further details and help with these projects, you can write to us in the comments section given below. Here is a question for you, what is VHDL?

Photo Credit

  • VLSI projects by ensemble-tech

Share This Post:

Arduino Uno Projects

Comments are closed.

  • Electronics
  • Communication
  • Free Circuits
  • Interview Questions
  • ECE Projects
  • EEE Projects
  • Project Ideas
  • Resistor Color Code Calculator
  • Ohms Law Calculator
  • Circuit Design
  • Infographics

IMAGES

  1. VLSI Projects For ECE

    research projects in vlsi

  2. VLSI Circuit and System Design

    research projects in vlsi

  3. VLSI Projects for Final Year ECE Students

    research projects in vlsi

  4. Academic Research Presentation

    research projects in vlsi

  5. A Modular Digital VLSI Flow for High-Productivity SoC Design

    research projects in vlsi

  6. 100+ VLSI Projects for Engineering Students

    research projects in vlsi

VIDEO

  1. CRI Academy: Unlocking Knowledge, Insights, and Skills in Technology Transfer and Entrepreneurship

  2. Sliding mode control of an Three phase Induction Machine Matlab simulink Electrical

  3. Bimetallic nanoparticles COMSOL Analysis

  4. HELIOSTAT position design solar power plants matlab code

  5. 6 DOF model of a UAV on MATLAB Simulink communication

  6. Microstrip patch antenna array 1X8 HFSS Ansys project Antenna

COMMENTS

  1. VLSI for Next Generation CE

    The current research in VLSI explores emerging trends and novel ideas and concepts covering a broad range of topics in the area of VLSI: from VLSI circuits, systems, and design methods, to system-level design and systemon- chip issues, to bringing VLSI methods to new areas and technologies such as nano and molecular devices, MEMS, and quantum computing. Future design methodologies are also key ...

  2. Top 50 VLSI Projects Ideas: A Guide for Final Year Electronics

    For those seeking more advanced challenges, these projects delve into intricate VLSI applications: 21. Design of a Low Power Memory Controller. Imagine creating a memory controller that efficiently manages data storage and retrieval while being mindful of power consumption. 22. VLSI Design of IIR Filter.

  3. Circuits and VLSI Design

    2022 IEEE SYMPOSIUM ON VLSI TECHNOLOGY & CIRCUITS. A 17-95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm. Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen Tell, Brian Zimmer, William Dally, Tom Gray, Brucek Khailany.

  4. 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology

    Profile Information. Communications Preferences. Profession and Education. Technical interests. Need Help? US & Canada: +1 800 678 4333. Worldwide: +1 732 981 0060. Contact & Support. Follow.

  5. Robust Low Power VLSI

    The Robust Low Power VLSI Group, led by Professor Ben Calhoun, investigates research topics related to modern VLSI design. Among the many challenges facing circuit designers in deep sub-micron technologies, power and variation are perhaps the most critical. ... In this project, the seal whisker team is focused on understanding how seals sense ...

  6. IEEE Transactions on Very Large Scale Integration Systems

    Scope. IEEE Transactions on Very Large Scale Integration (VLSI) Systems covers design and realization of microelectronic systems using VLSI/ULSI technologies that require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems ...

  7. Exploring Cutting-Edge VLSI Final Year Projects

    VLSI projects allow students to work on real-world problems and gain insight into how their designs can impact various sectors. Innovation and Research: Final-year VLSI projects often involve cutting-edge research and innovation. Students can contribute to the development of new technologies and solutions that address emerging challenges in the ...

  8. Emerging VLSI Technologies for High performance AI and ML Applications

    The capabilities of artificial intelligence (AI) and machine learning (ML) algorithms are constantly expanding, necessitating efficient and high-performance hardware systems. We have investigated the creation of hardware accelerators based on VLSI that are intended to effectively manage the heavy workloads of machine learning jobs, also explored low-power VLSI architectures that preserve ...

  9. harvard VLSI lab

    The Harvard VLSI Research Group is involved in the design and analysis of a variety of digital, analog, and mixed-signal VLSI systems. High performance computing, signal processing and sensor applications require innovative solutions that may focus on semiconductor device physics, VLSI fabrication technology, circuit design, systems architecture, and/or application software.

  10. VLSI-SoC: Design Trends

    The VLSI-SoC 2020 proceedings present cutting-edge research on very large scale integration, low-power design of RF, and more. VLSI-SoC: Design Trends: 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers | SpringerLink

  11. 19223 PDFs

    Explore the latest full-text research PDFs, articles, conference papers, preprints and more on VLSI DESIGN. Find methods information, sources, references or conduct a literature review on VLSI DESIGN

  12. 15 Innovative VLSI Projects for Engineering Students in 2024

    15 Innovative VLSI Projects for Engineering Students in 2024. Rahul David. February 12, 2024. 7:46 am. 2340. VLSI is a fascinating field that involves designing and building integrated circuits with millions of transistors. VLSI is a rapidly growing field as the need for semiconductors is increasing day after day.

  13. VLSI Project

    VLSI Project. The VLSI Project was a DARPA -program initiated by Robert Kahn in 1978 [ 1] that provided research funding to a wide variety of university -based teams in an effort to improve the state of the art in microprocessor design, then known as Very Large Scale Integration (VLSI). The VLSI Project is one of the most influential research ...

  14. 150+ VLSI Projects for Engineering Students

    The list of VLSI projects based on VHDL code includes the following. 1). VGA Type Bouncing Ball Interfacing with Spartan3 Type FPGA for Image Processing Kit. The aim of this project is to design a smart system for VGA on VLSI technology. It uses VGA, bouncing ball, Spartan 3 type FPGA, and connecting wires.

  15. Latest Research topics in vlsi design

    VLSI PHD Projects. Our research interests cover low power processor architectures, low power circuit design techniques, analog and mixed signal circuit design, rapid prototyping of digital systems, reconfigurable processors, Digital arithmetic, advanced processor architectures, vlsi implementation of signal and image processing algorithms ...

  16. AI/ML algorithms and applications in VLSI design and technology

    The impact of AI on VLSI design was first demonstrated in 1985 by Robert. S. Kirk [15]. He briefly explained the scope and necessity for AI techniques in CAD tools at different levels of VLSI design. His paper included a brief on the existing VLSI-AI tools and stressed the importance of incorporating the expanded capabilities of AI in CAD tools.

  17. Implementation of AI in the field of VLSI: A Review

    The Very Large Scale Integration (VLSI) industry has started adapting the Artificial Intelligence (AI) techniques in design automation as it provides the opportunity to transform the whole chip design methodology. It has been seen that in System-On-Chip (SoC), in order to add ML algorithms to increase its efficiency, there is a need to reduce the existing power consumption of the hardware as ...

  18. 70+ VLSI Projects

    70+ VLSI Projects Electronics Projects which always in demand in engineering level and especially very useful for ECE and EEE students. So, it is always benefial for electronics student and professional to have such material to generate new ideas. ... This project describes an approach that is automated hardware design space research, through a ...

  19. High-Performance VLSI Architectures for Artificial Intelligence and

    indicating a sizable research gap in the sector (Goda, 2016). This chapter outlines the main issues driving this research, explains its goals, and emphasizes the importance of solving them to advance the state-of-the-art VLSI architectures for AI and ML applications. Despite the growth of research activities in this area, there

  20. Home [vlsiweb.stanford.edu]

    Stanford VLSI research group lead by Professor Mark Horowitz. STANFORD VLSI RESEARCH GROUP Home. People. Projects. Wiki. Welcome. We're a diverse group of EE students, working on digital and analog circuit design, microfluidics, medical imaging, and more. Take a look at the projects page to see some of the things we're working on.

  21. AI/ML Algorithms and Applications in VLSI Design and Technology

    We also briefly present the VLSI design flow and introduction to artificial intelligence for the benefit of the readers. We organized the paper as follows. Section 2 briefly discusses the existing review articles on AI/ML-VLSI. An overview of artificial intelligence and machine learning and a brief on different steps in the VLSI design and manu-

  22. VLSI Projects for Engineering and M.tech Students

    VLSI Projects for Engineering Students. VLSI Projects with abstracts for electronics engineering students are discussed below. VLSI projects 1). Transform of Discrete Wavelet-based on 3D Lifting. This project helps in providing highly precise images by using the coding of an image without losing its data.