vhdl positional assignment

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X <= (others => '0'); in vhdl

Can someone please help me understand X <= (others => '0'); in vhdl.

When to use it and what is significance of this kind of assignment.

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Aggregate of 2 vectors in VHDL

I am checking what I can and cannot do in aggregating and concatenating in VHDL.

while I can combine two vectors by concatenating them, I keep getting error if I use aggregate.

I saw one answer here shows it is possible.

Can someone explain why they are giving errors, or maybe it is the language which does not allow this?

I appreciate any suggestion.

here is my code. I marked the correct and the wrong lines.I use ModelSim. I comment/uncomment when checking to avoid multiple drivers.

• \$\begingroup\$ (U_BUS(3 downto 0), P_BUS(3 downto 0)); is an aggregation not a concatenation (e.g. T_BUS <= U_BUS & P_BUS; ). For the aggregate assignment you haven't specified the VHDL version, earlier than or -2008 type nybble_array is array (0 to 1) of std_logic_vector(3 downto 0); and (U_BUS, P_BUS) <= nybble_array'(T_BUS (7 downto 4), T_BUS (3 downto 0)); You need an element on the right for each element on the left. The type has to be discernible from context. The element type has to be the same. \$\endgroup\$ –  user8352 Commented Feb 7, 2018 at 19:50
• \$\begingroup\$ You are asking for decomposition, not aggregation ... I know that the LRM calls it "aggregate" in the BNF of target . That's because the LRM is somehow lazzy in reusing existing BNF rules. But the technical correct term is decomposition, when a aggregate appears on the left side of an assignment. \$\endgroup\$ –  Paebbels Commented Feb 10, 2018 at 22:57
• \$\begingroup\$ @Paebbels - IEEE Std 1076-2008 describes design model structural decomposition , VHDL is a hardware description language. The term is not found in the Glossary of Software Engineering Terms (IEEE Std 610.12-1990) of the era the VHDL standard was created while 610.12-2012 defines it as 2. the partitioning of a modeled function into its component functions . That doesn't fit well with assignment as an impenetrable basic operation (5.1). The VHDL Extended BNF describes syntax which for an aggregate remains the same whether used as an expression or assignment target. \$\endgroup\$ –  user8352 Commented Feb 16, 2018 at 18:32
• \$\begingroup\$ @user8352 I know what the text in VHDL LRM says. I'm the vise-chair of the IEEE P1076 working group ... The term aggregate mean "collection". That is true for the right hand side of an assignment, but not for the left hand side (LHS). The LHS is the reverse operation - a split operation. It is called decomposition or unpacking. The correct way in the VHDL LRM would be to have a e.g. decomposition BNF rule, that is an alias for the aggregate rule. Other parts of the LRM make heavy use of these BNF "redirects". \$\endgroup\$ –  Paebbels Commented Feb 16, 2018 at 18:45
• \$\begingroup\$ The issue is basic operation . Assignment is not a function. That's spelled 'vice'. Annex I - aggregate: ( B ) A kind of target of a variable assignment statement or signal assignment statement assigning a composite value. The target is then said to be in the form of an aggregate. The standard is internally consistent. \$\endgroup\$ –  user8352 Commented Feb 16, 2018 at 18:56

Use the VHDL-2008 Library in ModelSim and your error is resolved. VHDL-93/2002 packages don't support aggregating vectors like the way you have expressed.

• 1 \$\begingroup\$ There isn't a comma operator. An aggregate is an expression, requires parentheses and includes one or more positional or named associations separated by commas. The new -2008 feature is that array aggregate association elements can be the type of the aggregate itself in addition to the aggregate element type. Prior revisions only support association elements of the aggregate element type. The type of the aggregate, it's element type and index type (for named association) are derived from context. Aggregation not concatenation. Your solution works, your explanation needs work. \$\endgroup\$ –  user8352 Commented Feb 8, 2018 at 1:51

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Designing Circuits with VHDL

1. introduction, 2. combinational circuits, signal assignments in vhdl.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fullAdder is     port(  A,B: in  std_logic;  -- input bits for this stage            Ci:   in  std_logic; -- carry into this stage            S:    out std_logic; -- sum bit            Co:   out std_logic  -- carry out of this stage     ); end fullAdder; architecture a1 of fullAdder is begin     S <= A xor B xor Ci;     Co <= (A and B) or ((A xor B) and Ci); end a1;

Processes and Conditional Statements

if a = '0' then     x <= a;     y <= b; elsif a = b then     x <= '0';   y <= '1'; else     x <= not b; y <= not b; end if;

Every signal that is assigned a value inside a process must be defined for all possible conditions.

Case Statements

Structural vhdl, 3. sequential circuits.

busy   is high when the circuit is in the middle of performing an operation;             while busy is high, the insert and delete inputs are ignored; the             outputs are not required to have the correct values when busy is high empty     is high when there are no pairs stored in the priority queue; delete             operations are ignored in this case full      is high when there is no room for any additional pairs to be stored;             insert operations are ignored in this case

• For adjacent pairs in the bottom row, the pair to the left has a key that is less than or equal to that of the pair on the right.
• For pairs that are in the same column, the key of the pair in the bottom row is less than or equal to that of the pair in the top row.
• In both rows, the empty blocks (those with dp =0) are to the right and either both rows have the same number of empty blocks or the top row has one more than the bottom row.

entity priQueue is     Port (clk, reset : in std_logic;           insert, delete : in std_logic;           key, value : in std_logic_vector(wordSize-1 downto 0);           smallValue : out std_logic_vector(wordSize-1 downto 0);           busy, empty, full : out std_logic     );    end priQueue; architecture a1 of priQueue is constant rowSize: integer := 4; -- local constant declaration type pqElement is record     dp: std_logic;     key: std_logic_vector(wordSize-1 downto 0);     value: std_logic_vector(wordSize-1 downto 0); end record pqElement; type rowTyp is array(0 to rowSize-1) of pqElement; signal top, bot: rowTyp; type state_type is (ready, inserting, deleting); signal state: state_type; begin     process(clk) begin         if rising_edge(clk) then             if reset = '1' then                 for i in 0 to rowSize-1 loop                     top(i).dp <= '0'; bot(i).dp <= '0';                 end loop;                 state <= ready;             elsif state = ready and insert = '1' then                 if top(rowSize-1).dp /= '1' then                     for i in 1 to rowSize-1 loop                         top(i) <= top(i-1);                     end loop;                     top(0) <= ('1',key,value);                     state <= inserting;                 end if;             elsif state = ready and delete = '1' then                 if bot(0).dp /= '0' then                     for i in 0 to rowSize-2 loop                         bot(i) <= bot(i+1);                     end loop;                     bot(rowSize-1).dp <= '0';                     state <= deleting;                 end if;             elsif state = inserting or state = deleting then                 for i in 0 to rowSize-1 loop                     if top(i).dp = '1' and                         (top(i).key < bot(i).key                          or bot(i).dp = '0') then                         bot(i) <= top(i); top(i) <= bot(i);                     end if;                end loop;                 state <= ready;             end if;         end if;     end process;     smallValue <= bot(0).value when bot(0).dp = '1' else                   (others => '0');     empty <= not bot(0).dp;     full <= top(rowSize-1).dp;     busy <= '1' when state /= ready else '0'; end a1;

4. Functions and Procedures

package commonConstants is     constant lgWordSize: integer := 4;        constant wordSize: integer := 2**lgWordSize; end package commonConstants; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.commonConstants.all; entity firstOne is     Port (a: in std_logic_vector(0 to wordSize-1);           x: out std_logic_vector (lgWordSize downto 0)      ); end firstOne; architecture a1 of firstOne is procedure encode(x: in std_logic_vector(0 to wordSize-1);                 indx: out std_logic_vector(lgWordSize-1 downto 0);                 errFlag: out std_logic) is -- Unary to binary encoder. -- Input x is assumed to have at most a single 1 bit. -- Indx is equal to the index of the bit that is set. -- If no bits are set, errFlag bit is made high. -- This is conceptually simple. -- --        indx(0) is OR of x(1),x(3),x(5), ... --        indx(1) is OR of x(2),x(3), x(6),x(7), x(10),x(11), ... --        indx(2) is OR of x(4),x(5),x(6),x(7), x(12),x(13),x(14(,x(15),... -- -- but it's tricky to code so it works for different word sizes. type vec is array(0 to lgWordSize-1) of std_logic_vector(0 to (wordSize/2)-1); variable fOne: vec; variable anyOne: std_logic_vector(0 to wordSize-1); begin     -- fOne(0)(j) is OR of first j bits in x1,x3,x5,...     -- fOne(1)(j) is OR of first j bits in x2,x3, x6,x7, x10,x11,...     -- fOne(2)(j) is OR of first j bits in x4,x5,x6,x7, x12,x13,x14,x15,...     for i in 0 to lgWordSize-1 loop         for j in 0 to (wordSize/(2**(i+1)))-1 loop                        for h in 0 to (2**i)-1 loop                 if j = 0 and h = 0 then                     fOne(i)(0) := x(2**i);                 else                     fOne(i)((2**i)*j+h) := fOne(i)((2**i)*j+h-1) or                                            x(((2**i)*(2*j+1))+h);                 end if;             end loop;         end loop;         indx(i) := fOne(i)((wordSize/2)-1);     end loop;     anyOne(0) := x(0);     for i in 1 to wordSize-1 loop         anyOne(i) := anyOne(i-1) or x(i);     end loop;     errFlag := not anyOne(wordSize-1); end procedure encode; function firstOne(x: std_logic_vector(0 to wordSize-1))                         return std_logic_vector is -- Returns the index of the first 1 in bit string x. -- If there are no 1's in x, the value returned has a -- 1 in the high order bit. variable allZero: std_logic_vector(0 to wordSize-1); variable fOne: std_logic_vector(0 to wordSize-1); variable rslt: std_logic_vector(lgWordSize downto 0); begin     allZero(0) := not x(0);     fOne(0) := x(0);     for i in 1 to wordSize-1 loop         allZero(i) := (not x(i)) and allZero(i-1);         fOne(i) := x(i) and allZero(i-1);     end loop;     encode(fOne,rslt(lgWordSize-1 downto 0),rslt(lgWordSize));     return rslt; end function firstOne; begin     x <= firstOne(a); end a1;

5. Closing Remarks

VHDL Component and Port Map Tutorial

Table of Contents

VHDL Port Map and Component

Component is a reusable VHDL module which can be declared with in another digital logic circuit using Component declaration of the VHDL Code. This helps to implement hierarchical design at ease.

Instead of coding a complex design in single VHDL Code. we can divide the code in to sub modules as component and combine them using Port Map technique.

VHDL Port Map is the Process of mapping the input/ Output Ports of Component in Main Module.

Port Map Block Diagram

There are 2 ways we can Port Map the Component in VHDL Code. They are

• Positional Port Map
• Nominal Port Map

Positional Port Map maps the formal in/out port location with actual in/out port without changing its location.

For example:

Nominal Port Map assign the formal parameter with actual parameter as shown below.

Let’s Create sample Component and Port Map in Main VHDL Module.

Here we Construct 2 to 1 Mux and Port Map the 2 to 1 mux component to implement 4 to 1 mux.

Port Map Example: VHDL Code for 2 to 1 Mux

The 2 to 1 mux can be port mapped in the 4 to 1 mux VHDL code by declaring it as component.

VHDL Code for 4 to 1 mux using 2 to 1 mux

In the above code we implemented positional port mapping technique by mapping at exact port location.

same can be declared with nominal Port mapping as shown below

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6 thoughts on “VHDL Component and Port Map Tutorial”

its so good best wishes. M.Mahdi

This should be other way i think especially portmap

c1: sub_module port map(A => x, B => y , S0 => s, m1 => z); (x => A, y => B , s => S0, z => m1)

c2: sub_module port map(C => x, D => y, S0 => s, m2 => z);

c3: sub_module port map(m1 => x, m2 => y, S1 => s, Z => z);

This is the most helpful example of how to use components and port maps that I have seen. Thank you.

Really helpful, thanks!

This is very helpful, Thanks

Leave a Reply Cancel reply

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VHDL Concurrent Conditional Assignment

The Conditional Signal Assignment statement is concurrent because it is assigned in the concurrent section of the architecture. It is possible to implement the same code in a sequential version, as we will see next.

The conditional signal assignment statement is a process that assigns values to a signal.

It is a concurrent statement; this means that you must use it only in concurrent code sections.

The statement that performs the same operation in a sequential environment is the “ if ” statement.

The syntax for a conditional signal assignment statement is:

This is a simple example of a two-way mux as reported here:

The output “ a ” is equal to “ b ” when the selector “ c ” is “1” else is equal to “ d ”

Concurrent Conditional Signal Assignment Example 1

This example extends the previous one. This is a 4-way mux, implemented as concurrent code.

The architecture declarative section is empty. As you can notice, we don’t care about how the mux is implemented.

In this moment we don’t’ talk about logic gate, and or nand ect, we are describing the behavior of circuit using a high level description.

A graphical representation can be this one.

It is up to the synthesizer to implement the best architecture on the selected technology in terms of logic gates. In fact if you are using FPGA the synthesizer will use LUT to map the VHDL functions, if you are implementing an ASIC the synthesized logic will depend on differ technology and will be implemented using, for instance, NAND, OR, NOR gate, depending on the technology.

Running the RTL compiler on Altera Quartus II , this is the output of the RTL viewer, if we try to layout this mux4 .

As clear, the RTL translation is implemented in terms of AND gate and 2-way mux. The output “ e ” is generated by cascading 3 two-way mux.

This is the output of the Altera MAP viewer selecting Cyclone IV FPGA technology. Our mux4 is implemented using LOGIC_COMB_CELL Look Up Table present in the Cyclone IV FPGA . This example should clarify the meaning of “technology dependent”.

Concurrent Conditional Signal Assignment Example 2

This example is the same 4-way mux as the previous one, in which we used a different syntax to implement the selector. In this case, we have introduced the statement “with select”.

In the architecture declarative section, we declared a signal “ sel ” of type integer used to address the mux. The signal “ sel ” is coded as binary to integer.

The statement “ with select ” allows compacting the syntax of the mux code. Note the introduction of the “ other ” keyword. It is necessary because the mux assignment cover only 3 of the 2^32 possible integer values. If we try to layout the code, it is interesting to see how RTL viewer interprets the VHDL code:

This case is different from the previous one. We can notice that the VHDL relative to the signal sel is decoded in order to implement mux selection and that the output mux is implemented as 4-way mux. So the RTL view of the RTL code is totally different from the previous one.

The FPGA used in this example is the same as the previous example, in fact the output of Altera MAP viewer have the same implementation of the previous RTL code as clear if we make a comparison between the two implementations.

These two examples should clarify the meaning of behavioral. We have seen two different implementations of a simple mux mapped on the same hardware :

implementation of different RTL code can generate the same hardware logic.

Of course, gaining the sensibility to write good VHDL/RTL code is only a matter of time and experience . If you will follow the course, you will find good advices in order to gain all the shortcuts useful reduce this amount of time.

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Assign values to an array partially in VHDL?

I have an array in VHDL of the form,

I wish to assign values to this array such that only one bit of each index is initialized. I suspected something like this will work,

But it gives the following error :-

In some sense, this is like a 2D matrix and I wish to initialize just one column completely. What can be done besides assigning the bits one by one?

2 Answers 2

You are receiving the first and second errors because your type is declared:

but your assignment to the signal which instances this type is using:

You should choose either to or downto for both.

The last error is because you are assigning (others => '0') , which is only applicable to vectors of bits, to a single bit. If you want to make that particular bit '0' , just assign it to '0' .

More generally, the syntax cache_array(15 downto 0)(33) is not meaningful.

If, per your comment and updated question, you want to assign one particular bit in every array element, you will have to use a loop of some kind:

Inside a process:

Outside a process as a concurrent assignment:

Note also that if you implement assignment of only one bit, the tools are unlikely to infer use of a block memory element for this functionality.

• I want to make that particular bit '0' for all indices of the array. I tried this comparisons(15 downto 0)(32) <= '0'; but I get an error Cache.vhd:65:28: static constant violates bounds . –  martianwars Commented Nov 21, 2016 at 15:25
• @KalpeshKrishna OK, I was just trying to explain why your code was causing errors. Please see my edit. –  scary_jeff Commented Nov 21, 2016 at 15:29
• I didn't know about these generate statements. All this does produce synthesizable code right? This looks really useful! –  martianwars Commented Nov 21, 2016 at 15:32
• @KalpeshKrishna Yes, loops and generate statements are synthesizable. Note that both of these sorts of loops are unrolled, so the loop bounds must be known at synthesis time. –  scary_jeff Commented Nov 21, 2016 at 15:36
• Also, do these happen in parallel in hardware? Or do they work in a sequential combinational manner? –  martianwars Commented Nov 21, 2016 at 15:37

Caution should be used in the generate loop method scary_jeff shows. concurrent statement in the generate loop will result in a separate process with a separate driver in each generated block, meaning you can't assign (33) for cache_array(i) from another process without resolving to a meta value.

The generate loop method is not generally useful without describing your entire cache operation in a single process.

There's also a third method using AND masking familiar to those with a programming background used to set cache_array(i)(33) to '0':

Because it required defining an "and" operator for type CacheArray, it lead to producing a to_string function for type CacheArray as well, which can tell us the contents of your cache:

The first cache value is the initial value, the second is the result of the "and" mask (note I initially filled cache_array with '1's to show the "and" worked).

You could add additional field separators for your cache word to make it easier to read and along with things like specific radix usage, noting you're responsible for calculating the retval string length properly and managing the retval pointer (retptr) in the to_string function. You could go as far as to add an output header. You could also organize output on a cache line basis. ...

In addition to report statements textio can be used to allow finer control of output and redirection to a text file. Either can allow you to observe cache state without resorting to reading waveform displays.

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