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Cmos low-dropout voltage regulator design trends: an overview.

1. Introduction

2. background, 2.1. overview of different categories of voltage regulators, 2.2. linear regulator scheme, 2.3. low-dropout (ldo) voltage regulator, 2.4. ldo design parameters, 3. ldo design topologies, 3.1. aldo design topologies, 3.1.1. folded compensation cascode topology, 3.1.2. buffer impedance attenuation topology, 3.1.3. current steering—fast transient ldo, 3.1.4. current-mode feedback buffer amplifier-based ldo, 3.1.5. high-speed compact output driver-based ldo, 3.1.6. supercapacitor assisted ldo, 3.1.7. fast-response adaptive-phase ldo, 3.1.8. feedforward compensated high-voltage linear regulator ldo, 3.1.9. high power supply rejection linear regulator ldo, 3.1.10. concurrent bulk modulation and forward body bias, 3.1.11. current-mode feedforward ripple canceller, 3.1.12. negative charge pump-enhanced (ncpe) ldo, 3.1.13. low-vdd inverting buffer with efficient feedforward path, 3.1.14. multistage error amplifier and prdtra-based ldo, 3.1.15. switched rc bandgap reference ldo, 3.1.16. voltage difference to time converter with direct output feedback, 3.1.17. performance comparison of aldo, 3.2. dldo design topologies, 3.2.1. proportional derivative (pd) compensation and sub-lsb duty control, 3.2.2. fully standard cell-based digital ldo, 3.2.3. coarse–fine dual loop digital ldo, 3.2.4. event-driven explicit time-coding architecture-based dldo, 3.2.5. beat-frequency quantizer and vco-based dldo, 3.2.6. time-to-digital converter (tdc)-based dldo, 3.2.7. performance comparison of dldo, 3.3. hd-ldo design topologies, 3.3.1. scan reconfigurable hybrid ldo, 3.3.2. bandgap reference-based hybrid ldo, 3.3.3. active ripple suppression-based hd-ldo, 3.3.4. switched-mode-control-based hybrid ldo, 3.3.5. exponential-ratio array (era)-based hybrid ldo, 3.3.6. performance comparison of hd-ldo, 4. conclusions, author contributions, institutional review board statement, informed consent statement, data availability statement, conflicts of interest.

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Click here to enlarge figure

References	Process (µm)	I (mA)	V (V)	V (V)	C (µF)	I (µA)	(mV)	(mV)	Load reg. (mV/mA)	Line reg. (mV/V)	Current Efficiency (%)	Active Area (mm )	PSR (dB)	Topology	FOM # (ps)
[ ]	0.25	50	2–2.5	1.5–1.97	0.05	100	0.47	530	0.08	N/A	99.8	0.23	43 @ 30 KHz	Current Feedback Amplifier	940
[ ]	0.35	200	2.0	1.8	1.0	20	0.2	200	34	2	99.8	0.264	340 @ ILM	Buffer Impedance Attenuation	100
[ ]	0.35	150	2.0	1.8	1.0	27	0.2	200	10	0	60	0.409	40 @ 20 KHz	Folded Cascade Topology	0.01
[ ]	0.35	100	3–5	2.8	1	59–189	3	2200	0.025	13.5	99.8	N/A	>56 (0 Hz–100 Hz)	Current Steering Approach	17.7
[ ]	0.65	30	2.5	1	39	10	195	50	0.2	0	80.3	0.154	2.8 @ 100 mHz	Adaptive Phase Scheme	0.085 and 0.08 n *
[ ]	0.25	100	N/A	1–3.3	Capless	40	N/A	230	N/A	N/A	N/A	0.21	50 @ 10 KHz	Sample and Hold Switched RC Filter	N/A
[ ]	0.065	45	0.6	0.5	10	21	44	100	0.047	1	99.95	0.045	N/A	Negative Charge Pump	0.1037
[ ]	0.18	11	1.3	1.09	N/A	276	45	210	0.015	0.6	N/A	0.105	−54 @ 10 MHz	Dual Feedback Structure with Charge Pump	10.49 and 0.677 mV **
[ ]	0.18	0	70	66	0.066	288	0.17	4000	1.7	90	99.71	0.15	N/A	Feedforward Compensated Method	0.03
[ ]	0.055	10	0.8	0.6	1	0.016	70	200	1.05	0.5	N/A	0.042	42.7 @ 50 KHz	Differential Flipped Voltage Follower	11.4
[ ]	0.04	100	1.1–1.9	0.2–1.1	1	56	28	900	0.176	0.857	99.94	0.375	−60 @ 1 MHz	Multistage Error Amplifier with TAPG	157
[ ]	0.5	600	1.5–5.0	1.3–4.8	5.1 × 10	16.5	514	200	0.011	0.156	99.95	0.082	−26.7 @ 1 MHz	Low-VDD Inverting Buffer	0.00012 and 1.42 ns.mV ***
[ ]	0.65	60	0.6–1.2	0.5–1.15	10	0.1–10	111	100	N/A	N/A	99.99	0.086	N/A	Voltage Difference to Time Converter	0.000202 and 0.182 fF ****

References	[ ]	[ ]	[ ]	[ ]	[ ]	[ ]
Technology (nm)	28	65	65	65	65	65
V (V)	1.1	0.7–1.2	0.5–1	0.6–1.2	0.5–1	0.7–1.1
V (V)	0.9	0.6–1.1	0.45–0.95	0.4–1.1	0.3–0.45	0.65–1.05
V (mV) @ I (mA)	120@180			108@50		371@80
I (mA)	200	25	0.0072–3.511	100	2	120
I (mA)	0.2	0.006	0.012–0.216	0.1–1.07	0.014	0.495
Current Peak Efficiency (%)	99.94	99.97	96.3	99.5	99.8	99.6
C (nF)	23.5	1	0.4	0.04	0.4	0.5
Load Regulation (mV/mA)	N/A	0.04	N/A	0.638	<5.6	0.6
Line Regulation (mV/V)	N/A	0.78	N/A	N/A	2.3	0.5
PSRR (dB)	N/A	N/A	N/A	–38@1MHz	N/A	N/A
Active Area (mm )	0.021	0.014	0.029	0.0374	0.0023	0.017
Response Time, T (ns)	N/A	N/A	N/A	N/A	15.1	2.1
FOM #	7.75 (ps)	2.17 (ps)	1.11 (ps)	1.38 (ps)	199 (ps)	8.7 (ps)
Circuit Topology	Current-mirror flash analog to digital converter (ADC)	Logic-Threshold Triggered Comparator	Event-Driven Explicit Time-Coding	Beat-Frequency Quantizer and VCO	PD Compensation and Sub-LSB Duty Control	Time-to-Digital Converter (TDC)

References	[ ]	[ ]	[ ]	[ ]	[ ]
Technology (nm)	180	130	130	65	500
Input Voltage, V (V)	1.43–2.0	0.6, 1.1–1.2	N/A	0.8–1.0	2.2–5
Output Voltage, V (V)	1.0–1.57	0.5–0.55, 0.8–1.1	N/A	0.75–0.95	2–4.85
V (mV)	N/A	N/A	N/A	50	120 (P-type)
Maximum I (mA)	100	12	5	0.01–40	300
Quiescent Current, IQ (mA)	1	N/A	0.057	0.12	0.050
Current Peak Efficiency (%)	99.11	98.5 (R), 98.64 (L)	98.86	99.7	N/A
C (nF)	Cap-Free	0.5	0.5	Cap-Free	1
Load Regulation (mV/mA)	0.01	<2.67	N/A	N/A	0.003
Line Regulation (mV/V)	1	N/A	N/A	N/A	0.28
PSR (dB)	N/A	N/A	−9 to −34 @ 100 MHz	N/A	80 @0.1 MHz
Active Area (mm )	0.679	0.0818	N/A	0.175	N/A
FOM (ps) #	N/A	166(R), 244.8 (Linear) and 0.58 (R), 1.747(Linear) ns/mA ##	28.06 and 28.06 @ 100 MHz ###	0.0188	11

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Sobhan Bhuiyan, M.A.; Hossain, M.R.; Minhad, K.N.; Haque, F.; Hemel, M.S.K.; Md Dawi, O.; Ibne Reaz, M.B.; Ooi, K.J.A. CMOS Low-Dropout Voltage Regulator Design Trends: An Overview. Electronics 2022 , 11 , 193. https://doi.org/10.3390/electronics11020193

Sobhan Bhuiyan MA, Hossain MR, Minhad KN, Haque F, Hemel MSK, Md Dawi O, Ibne Reaz MB, Ooi KJA. CMOS Low-Dropout Voltage Regulator Design Trends: An Overview. Electronics . 2022; 11(2):193. https://doi.org/10.3390/electronics11020193

Sobhan Bhuiyan, Mohammad Arif, Md. Rownak Hossain, Khairun Nisa’ Minhad, Fahmida Haque, Mohammad Shahriar Khan Hemel, Omar Md Dawi, Mamun Bin Ibne Reaz, and Kelvin J. A. Ooi. 2022. "CMOS Low-Dropout Voltage Regulator Design Trends: An Overview" Electronics 11, no. 2: 193. https://doi.org/10.3390/electronics11020193

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University of Illinois Urbana-Champaign

Comparative analysis of analog LDO design

Lee, dong joon.

https://hdl.handle.net/2142/95513 Copy

Description

Analog low dropout (LDO)
Digital low dropout (LDO)

Owning Collections

Graduate dissertations and theses at illinois primary, dissertations and theses - electrical and computer engineering, manage files, edit collection membership, edit metadata, edit properties.

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IMAGES

Design of LDO Regulator with Efficient Error Amplifier
(a) Conventional LDO design. (b) Proposed LDO design.
(PDF) An efficient PMOS-based LDO design for large loads
3: LDO Design process
(PDF) Design of LDO for Low Power Biomedical Applications
(PDF) Design of A low-dropout or LDO Regulator

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COMMENTS

PDF The Design of An LDO Regulator [The Analog Mind]
The Design of An LDO Regulator Many mixed-signal systems incorpo-rate LDO regulators to generate local supply voltages for various building blocks. LDOs isolate the circuits from one another's noise and from the noise on the global supply, V DD. For optimum performance, the design of each LDO is tailored to the particu-lar cell that it feeds.
PDF Design and realization of low dropout voltage regulators in PMIC for
Amongst all the design metrics of LDO, a fast load transient response with small ... This thesis also analyzes its design robustness in terms of stability and offset. A low-cost trim method is also introduced to achieve a high yield for potential production. This LDO with high swing dynamic
PDF Low-dropout Regulator With Transient Response
Dropout (LDO) regulators, which are a pivota. part of the power systems in such devices. However, removing the large output capacitor. LDOs to allow for full chip integration comes at a cost as it lea. and undershoots during load transients and degrades AC stability. r whichuse.
PDF CURRENT EFFICIENT, LOW VOLTAGE, LOW DROPOUT REGULATORS
A THESIS Presented to the Academic Faculty by ... Physical design issues are discussed within the context of existing process technologies, such as CMOS, bipolar, and biCMOS processes. This is followed by a ... LDO Implications 155 8.4 Conclusion and Recommendations 156 APPENDICES 158 ...
PDF Study and Design of Low Drop-Out Regulators
I. Introduction 1.1 Definition. A series low-drop-out regulator is a circuit that provides a well-specified and stable dc voltage [1] whose input to output voltage difference is low [2]. The drop-out voltage is defined as the value of the input/output differential voltage where the control loop stops regulating.
PDF Design of sub 1V capacitorless Low dropout regulator in 65NM technology
In this thesis, design of Sub 1V capacitorless low power LDO regulator with its associated trade-offs is presented. Design considerations for LDO There are three main considerations for VLSI design - Power, Performance, Area. There are various figures of merit for Voltage regulators which directly impact these parameters.
PDF A Low-Power, High-Bandwidth LDO Voltage Regulator with No External
A low-dropout (LDO) voltage regulator for low-power applications is designed without an external capacitor for compensation. The regulator has two stages, the first a folded ... Title: Analog IP Design Manager Thesis Supervisor: Joel Dawson Title: Carl Richard Soderberg Professor of Power Engineering . Contents
PDF Low Drop-Out (LDO) Linear Regulators: Design Considerations and Trends
Low Dropout Voltage Regulator (LDO) The LDO act as a variable resistor that is placed between input power source and the load in order to drop and control the voltage applied to the load. Compared to DC‐DC switching regulators, LDOs are: Of continuous operation. Easier to use.
PDF Design, Simulation and Layout of Low Drop- Out (LDO) Voltage ...
LDO. We can also design an ultra-low quiescent current low-dropout regulator with small output voltage variation and improved load regulation. References Tiikkainen M, "LDO Voltage Regulator for On-Chip Power Management," University of Oulu, Department of Electrical Engineering. Master's Thesis, 86p. 2014.
PDF LDO Thesis
LDO Thesis. AGENDA • What is a Linear Regulator • LDO Introductions • LDO'S Terms and Definitions ... The design limit of the current source defines the maximum load current the regulator can source and still maintain regulation. • The output voltage is controlled using a feedback loop, which requires some type of compensation to ...
PDF A low jitter PLL using high PSRR low-dropout regulator
This thesis presents low power and low jitter phase locked loop (PLL) design using proposed LDO regulator and active loop ﬁlter on 110nm CMOS technology node and with 1V power supply voltage. In order to reduce jitter, the supply voltage is regulated by low-dropout (LDO) regulator which regulates supply voltage with minimal noise and delivers
Design and realization of low dropout voltage regulators in PMIC for
This thesis also analyzes its design robustness in terms of stability and offset. A low-cost trim method is also introduced to achieve a high yield for potential production. This LDO with high swing dynamic biasing impedance-attenuation buffer has been fabricated in 0.18-μm HV CMOS process. The silicon size of the LDO is 137000 μm2.
PDF Innovative Solutions for LDO Design Challenges in the Era of Expanding
Innovative Solutions for LDO Design Challenges in the Era of Expanding 3D NAND Flash Arrays: A Multi-Loop FVF Driver Topology Approach Thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in Electronics and Communication Engineering by Research by Ashish Papreja 2020702011 [email protected] ...
PDF LDO with low quiescent current OTA and capacitance scaling circuit
3.5 Design of Capacitor based LDO employing adaptive biasing 11 3.6 Capacitance Scaling circuit 13 3.7 Small Signal Model of Capacitance scaling circuit 14 3.8 Proposed Capacitorless LDO 15 3.9 Op-Amp based BGR with start-up circuit 16 3.10 Reference Voltage variation with temperature 17 3.11 Small signal model of LDO 18
CMOS Low-Dropout Voltage Regulator Design Trends: An Overview
Systems-on-Chip's (SoC) design complexity demands a high-performance linear regulator architecture to maintain a stable operation for the efficient power management of today's devices. Over the decades, the low-dropout (LDO) voltage regulator design has gained attention due to its design scalability with better performance in various application domains. Industry professionals as well as ...
PDF Capacitor-less Low Dropout Regulator (LDO)
The thesis comprises of 8 chapters. Chapter 2 has the background of the regulator and it's performance parameters. Chapter 3 shows the challenges in the capless LDO. Chapter 4 guides us about the design method and techniques for the appropriate design. Chapter 5 has the building block designs that requires for a system of capless LDO i.e.
Design of Low Dropout (LDO) Regulators
<P>Low dropout (LDO) regulators are widely used in portable electronic devices because they occupy small chip and printed circuit board (PCB) areas. These regulators are appropriate for low-power applications because of heat dissipation. This chapter first introduces the basic LDO regulator, and then, presents concerns over compensation for loop stability to develop dominant pole compensation ...
The Design of An LDO Regulator [The Analog Mind]
Many mixed-signal systems incorporate LDO regulators to generate local supply voltages for various building blocks. LDOs isolate the circuits from one another's noise and from the noise on the global supply, <inline-formula><tex-math notation="LaTeX">${V}_{\\text{DD}}$</tex-math></inline-formula> . For optimum performance, the design of each LDO is tailored to the particular cell that it ...
PDF Approach to the Implementation and Modeling of LDO-Assisted DC-DC
Abstract—This paper presents the design of an LDO-assisted DC-DC voltage regulator in Cadence Virtuoso® based on a 350-nm CMOS technology. This kind of voltage regulator consists of a switching converter together with a classic or LDO (low drop-out) linear voltage regulator. While the linear regulator provides
PDF Design and Layout Automation for LDO Regulators
Mohamed Essam Sayed Hussein, Design and Layout Automation for LDO Regulators, Master of Science thesis, Ain Shams University, 2014. Analog design has always been a more involved process than digital design. it takes to longer to master so it comes the importance of Analog Design Automation (ADA) to short the time to market and to reach to the
Comparative analysis of analog LDO design
Description. The presented research analyses different topologies of low dropout (LDO) regulator, mostly focusing on different frequency compensation schemes and power supply rejection analysis. This thesis discusses different analog LDO topologies and analyzes how they achieve stability using small signal analysis and related equations.
PDF Nanyang Technological University
Nanyang Technological University
PDF Design of a low voltage,low drop-out (LDO) voltage cmos regulator
A Low-drop-out (LDO) regulator is a DC linear voltage regulator which can operate with a very small input-output differential voltage. The demand for the low-voltage, low drop out (LDO) regulators is increasing because of the growing demand of portable electronics, i.e., mobile phones, pagers, laptops, etc as well as industrial and automotive ...