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Altera DE2-115 Development Board
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The DE2 series has consistently been at the forefront of educational development boards by distinguishing itself with an abundance of interfaces to accommodate various application needs. Extending its leadership and success, Terasic announces the latest DE2-115 that features the Cyclone IV E device . Responding to increased versatile low-cost spectrum needs to be driven by the demand for mobile video, voice, data access, and the hunger for high-quality images, the new DE2-115 offers an optimal balance of low cost, low power, and a rich supply of logic, memory, and DSP capabilities .
Altera DE2-115 Development Board Pinout
The DE2-115 Board provides one 40-pin expansion header. The header connects directly to 36 pins of the Cyclone IV E FPGA and also provides DC +5V (VCC5), DC +3.3V (VCC3P3), and two GND pins.
| Signal Name | FPGA Pin No | Description | I/O Standard |
| GPIO[0] | PIN_AB22 | GPIO Connection DATA[0] | Depending on JP6 |
| GPIO[1] | PIN_AC15 | GPIO Connection DATA[1] | Depending on JP6 |
| GPIO[2] | PIN_AB21 | GPIO Connection DATA[2] | Depending on JP6 |
| GPIO[3] | PIN_Y17 | GPIO Connection DATA[3] | Depending on JP6 |
| GPIO[4] | PIN_AC21 | GPIO Connection DATA[4 | Depending on JP6 |
| GPIO[5] | PIN_Y16 | GPIO Connection DATA[5] | Depending on JP6 |
| GPIO[6] | PIN_AD21 | GPIO Connection DATA[6] | Depending on JP6 |
| GPIO[7] | PIN_AE16 | GPIO Connection DATA[7] | Depending on JP6 |
| GPIO[8] | PIN_AD15 | GPIO Connection DATA[8] | Depending on JP6 |
| GPIO[9] | PIN_AE15 | GPIO Connection DATA[9] | Depending on JP6 |
| GPIO[10] | PIN_AC19 | GPIO Connection DATA[10] | Depending on JP6 |
| GPIO[11] | PIN_AF16 | GPIO Connection DATA[11] | Depending on JP6 |
| GPIO[12] | PIN_AD19 | GPIO Connection DATA[12] | Depending on JP6 |
| GPIO[13] | PIN_AF15 | GPIO Connection DATA[13] | Depending on JP6 |
| GPIO[14] | PIN_AF24 | GPIO Connection DATA[14] | Depending on JP6 |
| GPIO[15] | PIN_AE21 | GPIO Connection DATA[15] | Depending on JP6 |
| GPIO[16] | PIN_AF25 | GPIO Connection DATA[16] | Depending on JP6 |
| GPIO[17] | PIN_AC22 | GPIO Connection DATA[17] | Depending on JP6 |
| GPIO[18] | PIN_AE22 | GPIO Connection DATA[18] | Depending on JP6 |
| GPIO[19] | PIN_AF21 | GPIO Connection DATA[19] | Depending on JP6 |
| GPIO[20] | PIN_AF22 | GPIO Connection DATA[20] | Depending on JP6 |
| GPIO[21] | PIN_AD22 | GPIO Connection DATA[21] | Depending on JP6 |
| GPIO[22] | PIN_AG25 | GPIO Connection DATA[22] | Depending on JP6 |
| GPIO[23] | PIN_AD25 | GPIO Connection DATA[23] | Depending on JP6 |
| GPIO[24] | PIN_AH25 | GPIO Connection DATA[24] | Depending on JP6 |
| GPIO[25] | PIN_AE25 | GPIO Connection DATA[25] | Depending on JP6 |
| GPIO[26] | PIN_AG22 | GPIO Connection DATA[26] | Depending on JP6 |
| GPIO[27] | PIN_AE24 | GPIO Connection DATA[27] | Depending on JP6 |
| GPIO[28] | PIN_AH22 | GPIO Connection DATA[28] | Depending on JP6 |
| GPIO[29] | PIN_AF26 | GPIO Connection DATA[29] | Depending on JP6 |
| GPIO[30] | PIN_AE20 | GPIO Connection DATA[30] | Depending on JP6 |
| GPIO[31] | PIN_AG23 | GPIO Connection DATA[31] | Depending on JP6 |
| GPIO[32] | PIN_AF20 | GPIO Connection DATA[32] | Depending on JP6 |
| GPIO[33] | PIN_AH26 | GPIO Connection DATA[33] | Depending on JP6 |
| GPIO[34] | PIN_AH23 | GPIO Connection DATA[34 | Depending on JP6 |
| GPIO[35] | PIN_AG26 | GPIO Connection DATA[35] | Depending on JP6 |
Features and Specifications
- Altera Cyclone® IV 4CE115 FPGA device
- Altera Serial Configuration device – EPCS64
- USB Blaster (onboard) for programming; both JTAG and Active Serial (AS) programming modes are supported
- 2MB SRAM
- Two 64MB SDRAM
- 8MB Flash memory
- SD Card socket
- 4 Push-buttons
- 18 Slide switches
- 18 Red user LEDs
- 9 Green user LEDs
- 50MHz oscillator for clock sources
- 24-bit CD-quality audio CODEC with line-in, line-out, and microphone-in jacks
- VGA DAC (8-bit high-speed triple DACs) with VGA-out connector
- TV Decoder (NTSC/PAL/SECAM) and TV-in connector
- 2 Gigabit Ethernet PHY with RJ45 connectors
- USB Host/Slave Controller with USB type A and type B connectors
- RS-232 transceiver and 9-pin connector
- PS/2 mouse/keyboard connector
- IR Receiver
- 2 SMA connectors for external clock input/output
- One 40-pin Expansion Header with diode protection
- One High-Speed Mezzanine Card (HSMC) connector
- 16x2 LCD module
In addition to these hardware features, the DE2-115 board has software support for standard I/O interfaces and a control panel facility for accessing various components. Also, the software is provided for supporting a number of demonstrations that illustrate the advanced capabilities of the DE2-115 board.
Note: To know more about specific features in detail, check out the DE2-115 board datasheet given at the bottom of this page.
DE2-115 Board Block Diagram
The basic block diagram of the DE2-115 board is shown below. You can check out the datasheet for more info on the device.
Power up the DE2-115 Board
The DE2-115 board comes with a preloaded configuration bitstream to demonstrate some features of the board. This bitstream also allows users to see quickly if the board is working properly.
To power up the board, perform the following steps:
1. Connect the provided USB cable from the host computer to the USB Blaster connector on the DE2-115 board. For communication between the host and the DE2-115 board, it is necessary to install the Altera USB Blaster driver software. If this driver is not already installed on the host computer, it can be installed as explained in the tutorial “ Getting Started with Altera's DE2-115 Board ” (DE2-115 board datasheet) which is linked on the bottom of the page. This tutorial is available in the directory DE2_115_tutorials on the DE2-115 System CD.
2. Turn off the power by pressing the red ON/OFF switch before connecting the 12V adapter to the DE2-115 board.
3. Connect a VGA monitor to the VGA port on the DE2-115 board.
4. Connect your headset to the line-out audio port on the DE2-115 board.
5. Turn the RUN/PROG switch (SW19) on the left edge of the DE2-115 board to the RUN position; the PROG position is used only for the AS Mode programming.
6. Recycle the power by turning the red power switch (on the DE2-115 board) OFF and ON again.
At this point you should observe the following:
- All user LEDs are flashing
- All 7-segment displays are cycling through the numbers 0 to F
- The LCD display shows “Welcome to the Altera DE2-115”
- The VGA monitor displays the image shown in Figure 2-4
- Set the slide switch SW17 to the DOWN position; you should hear a 1-kHz sound. Be careful of loud volume for avoiding any discomfort
- Set the slide switch SW17 to the UP position and connect the output of an audio player to the line-in connector on the DE2-115 board; on your speaker or headset you should hear the music played from the audio player (MP3, PC, iPod, or the like)
- You can also connect a microphone to the microphone-in connector on the DE2-115 board; your voice will be mixed with the music playing on the audio player.
The DE2-115 board comes with a Control Panel facility that allows users to access various components on the board from a host computer. The host computer communicates with the board through a USB connection. The facility can be used to verify the functionality of components on the board or be used as a debug tool while developing RTL code. This chapter first presents some basic functions of the Control Panel, then describes its structure in block diagram form, and finally describes its capabilities
JTAG Chain on DE2-115 Board
To use the JTAG interface for configuring an FPGA device, the JTAG chain on DE2-115 must form a close loop that allows the Quartus II programmer to detect the FPGA device. Shorting pin1 and pin2 on JP3 can disable the JTAG signals on the HSMC connector that will form a close JTAG loop chain on the DE2-115 board. To do that you need to flip the switch SW19 on the board to enable JTAG.
Applications
- high-speed search
- aerospace and defense
- medical electronics
- digital television
- consumer electronics
- industrial motor control
- scientific instruments
- cybersecurity systems, and wireless communications
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Using De2-115 board to run a project developed on a different board?
I am trying to run different open source projects/games on my DE2-115 Altera board, however, these projects are usually developed on different boards like: Xilinx Spartan 3, DE0, DE1, ...etc.
My question is, what are generally the things I need to change in such projects in order to make them successfully run on my board?
The first thing I usually do is to change board type and import my board's pin assignment file. But still the projects compile successfully but don't give the expected functionality. I'm using Quartus II design software.
Many thanks!
- Unn's answer below is correct, but I wanted to add that the default pin names (i.e. LEDR or SW ) for the Altera DE-series boards are generally the same, so projects built for a DE1 or DE2 should be fairly trivial to transfer to a DE2-115 (change the device and import the 115's pin assignments). – wilcroft Commented Nov 16, 2015 at 15:48
While this is a very broad question, in general, to port a project from one FPGA to another, it will likely take more than changing the board type and simply importing a pin assignments file. Here are a few things to consider:
- You do need to take the code, typically in a project, and either change the project to use the target FPGA or create a new project to use the target FPGA.
- You must make sure the target board has all the needed hardware components as the board the project was originally designed for. This includes buttons, switches, LEDs, seven segments, VGA/Video ports, Audio ports, etc. All that hardware must be at least available on the target board.
- If you are lucky and the same or comparable hardware is existent on the target port, you need to be sure the IO of the top level module of the code properly maps to the hardware on the target board. The original pin assignments for the original board are probably included, but you need to be sure you do these assignments for the target board so all IO goes where its supposed to. This can easily be more involved than simply importing a pin assignments file as you need to be sure the top level IO and the pin assignments file use the same net names, ie, Altera uses things like HEX0 for a seven segment, but if the top level IO calls this sseg0, the import will not properly assign the pins.
- In most cases (at least for things like video, audio and anything more complicated than an led or push button), the interfaced for the various components on the board will NOT be the same. Now you will have to modify the original code to use the target board's hardware instead of the original board's hardware.
- Not only the boards hardware, but some stuff inside the FPGA might not be compatible. If the project uses special IP cores, these will have to be replaced or modified to the target FPGA. This will take some effort for chips of different families (like a port from a Altera Cyclone III to an Altera Cyclone IV or Cyclone IV SE to Cyclone IV E) and even worse between manufacturers. So things might not even port, and if the target FPGA is much smaller than the original FPGA, the design might not even fit at all.
The short answer is that porting an FPGA project designed for one board to another can be alot more involved than simply opening the project and changing a setting or two; it really depends on the project, its original target and the new target you want to synthesize to.
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IMAGES
VIDEO
COMMENTS
DE2-115 Board I/O Pin Assignments: Switches, LEDs, and 7-Segment Displays. Table 1: Pin assignments for slide switches. Table 2: Pin assignments for pushbutton (debounced) switches. Table 3: Pin assignments for LEDs. Table 4: Pin assignments for 7-segment displays. Table 5: Pin assignments for clock inputs.
DE2-115 Board I/O Pin Assignments: Switches, LEDs, and 7-Segment Displays Table 1: Daughter Board Pin assignments Signal Name FPGA Pin No. Description SW3_DB PIN_AB22 Rocker Switch[3] SW2_DB PIN_AB21 Rocker Switch[2] SW1_DB PIN_AC21 Rocker Switch[1] ... Table 6: Pin assignments for clock inputs .
Altera DE2 Board Pin Table SRAM_WE_N PIN_AE10 SRAM Write Enable SRAM_OE_N PIN_AD10 SRAM Output Enable SRAM_UB_N PIN_AF9 SRAM High-byte Data Mask SRAM_LB_N PIN_AE9 SRAM Low-byte Data Mask SRAM_CE_N PIN_AC11 SRAM Chip Enable Signal Name FPGA Pin No. Description OTG_ADDR[0] PIN_K7 ISP1362 Address[0]
Chapter 2 Introduction of the Altera DE2-115 Board This chapter presents the features and design characteristics of the DE2-115 board. A photograph of the DE2-115 board is shown in Figure 2-1 Figure 2-2. ... or in the DE2_115_datasheets\VIDEO-DAC folder on the DE2-115 System CD. The pin assignments between the Cyclone IV E FPGA and the ADV7123 ...
In addition, all these clock inputs are connected to the phase locked loops (PLL) clock input pins of the FPGA to allow users to use these clocks as a source clock for the PLL circuit. The clock distribution on the DE2-115 board is shown in Figure 4-11. The associated pin assignments for clock inputs to FPGA I/O pins are listed in Table 4-5.
# File: D:\de2_pins\DE2_115_pin_assignments.csv # Generated on: Friday Feb 22 2019 # Note: The column header names should not be changed if you wish to import this .csv file into the Quartus Prime software.
Figure 3.7 shows the circuit diagram of the audio part of DE2. The pin assignment of the associated interface is shown in Table 3.2. PAGE 21. Using the System Table 3.2 Pin Assignment for Audio CODEC Using the LEDs and Switches 3-6 The DE2 Board provides 4 push buttons. All of the buttons are Schmitt Trigger de-bounced.
2.2.3 On-Chip Memory. The DE2-115 Computer includes a 8-Kbyte memory that is implemented in the Cyclone IV FPGA chip. This memory is organized as 8K x 8 bits, and spans addresses in the range 0x09000000 to 0x09001FFF. This memory is used as a character buffer for the video-out port, which is described in section 4.2.
Build your first project and program it into the DE2 board as shown in the video. The pin assignments file, DE2_115_pin_assignment.csv, can be downloaded from the lab website. Once the project is programmed into the DE2 board, verify that your project works by flipping Switches 0 and 1 and
DE2 115 Pin Assignment (1) - Free download as PDF File (.pdf), Text File (.txt) or read online for free. The document describes the pin assignments for various I/O components on the DE2-115 board, including slide switches, pushbuttons, LEDs, 7-segment displays, and clock circuitry. Table 4-1 lists the 18 slide switches on the board. Table 4-2 lists the 4 pushbuttons.
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The DE2-115 Board provides one 40-pin expansion header. The header connects directly to 36 pins of the Cyclone IV E FPGA and also provides DC +5V (VCC5), DC +3.3V (VCC3P3), and two GND pins. ... it can be installed as explained in the tutorial "Getting Started with Altera's DE2-115 Board" (DE2-115 board datasheet) which is linked on the ...
DE2-115 System Builder. DE2-115 System Builder - a powerful tool that comes with the DE2-115 board. This tool will allow users to create a Quartus II project file on their custom design for the DE2-115 board. The top-level design file, pin assignments, and I/O standard settings for the DE2-115 board will be generated automatically from this tool.
DE2-115 Datasheet(HTML) 36 Page - Altera Corporation: zoom in zoom out 36 / 116 page. 35. Table 4-1. Pin Assignments for Slide Switches. Signal Name. FPGA Pin No. Description. I/O Standard. SW[0] PIN_AB28. Slide Switch[0] Depending on JP7. ... DE2-115 with LCD Touch Panel and Camera Zilog, Inc. Z51F0811:
Altera DE2 Board Pdf User Manuals. View online or download Altera DE2 Board Getting Started Manual. ... The Top Level Verilog Module and Pin Assignment. 46. Chapter 5 First Lab: De2 Top-Level and Default Bitstream. 48. Lash. 49. Link. 57. ... Altera tPad DE2-115 ; Altera DE1-SoC ...
Touch Panel Altera tPad DE2-115 User Manual 43 pages. Tpad board with lcd touch panel and camera. Computer Hardware Altera DE2-70 User Manual 93 pages. Development and education board. Computer Hardware Altera Cyclone III FPGA User ...
Start an Analysis and Synthesis process, so that Quartus automatically collects the I/O pins from your project. Then, go to the Quartus Assignments menu and select Pins. You are presented with the list of the I/Os and you simply assign each of them the desired fpga pin. Refer to DE2 115 schematic to find out what fgpa pins are connected to ...
A web application to easily lookup pin assignments of the Altera DE2 board. - neelabhg/easy-de2-pin-assignments
23 3. Unn's answer below is correct, but I wanted to add that the default pin names (i.e. LEDR or SW) for the Altera DE-series boards are generally the same, so projects built for a DE1 or DE2 should be fairly trivial to transfer to a DE2-115 (change the device and import the 115's pin assignments). - wilcroft.
Terasic Inc. - Expertise in FPGA/ASIC Design
53Table 4-16Pin Assignments for ADV7123Signal NameFPGA Pin No.DescriptionI/O StandardVGA_R[0]PIN_E12VGA Red[0] Datasheet search, datasheets, Datasheet search site for Electronic Components and Semiconductors, integrated circuits, diodes, triacs and other semiconductors. ... DE2-115 Datasheet(HTML) 54 Page - Altera Corporation: zoom in zoom out ...
I'm attaching the file that I imported as my assignment file just for completeness of this thread. Its titled "DE2-115_pin_assignments.txt". i troubleshooted this by going through the whole pin assignment process manually I typed in each port assignment location for each input "that being each switch" and for each output "that being each LED".
DE2-115 Pin Assignment 1.Pin Assignments for Slide Switches 2. Pin Assignments for Push-buttons 3. ... Engineering 303 Digital Logic Design - Folsom Lake College · Note: The Altera DE2-115 User Manual can be found online and includes the complete list of pin assignments. Signal Name. Documents. THDB ADA - Mouser Electronics 日本 - 電子 ...